Could you post your flowgraph or UHD program, or the relevant excerpts? Are
the two RX channels being loaded simultaneously? Are you using timed
commands to start the RX and TX streams?

Nick

On Tue, Mar 6, 2018 at 11:52 AM Prager, Samuel M (334E) via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hello,
>
>
>
> We are interested in using the E312 as a phase-sensitive radar sounder and
> have run into an interesting issue.
>
>
>
> We are measuring (relative) cable length by estimating linear phase slope
> from a 10MHz chirp pulse and are using the following test setup (attached):
>
>
>
> We have set the appropriate AD9361 registers to keep the VCO/PLL dividers
> on so that RXA (data) and RXB (calibration) are phase coherent. We perform
> pulse averaging on each channel and match filter with the cal channel pulse
> (shorter cable).
>
>
>
> We have noticed that the phase measurements remain stable within <*1 cm* 99%
> confidence interval for successive trials with multiple re-tunings of the
> LO over long periods of time. However, we have found that if the FPGA bit
> file is unloaded (put in idle mode) and then reloaded (either through
> power-cycle or termination of UHD-based application), the measured phase
> slope jumps randomly.
>
>
>
> We’re really scratching our heads over this behavior… multiple trials on a
> given ‘cycle’ remain stable around a mean value, but that value jumps
> around from cycle to cycle in a seemingly random way.
>
>
>
> I have attached plots for two tests - the vertical black dotted lines are
> placed to show when the E312 FPGA image was cycled. Each data point is
> taken from a separate LO tuning (ie. tune to 400mhz, collect data, tune to
> 1ghz, wait, tune to 400mhz, collect data,…)
>
>
>
> Any ideas about where could possibly be coming from? Is there somewhere in
> the E312 initialization that the relative path between RXA and RXB may be
> changed non-deterministically?
>
>
>
> I really appreciate any help!
>
>
>
> Thank you,
>
>
>
> Sam
>
>
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