Greetings all! I'm working through spinning up on RFNoC on an E310 and I am running into a segfault when I try to run the fosphor example. The problem appears to happen in the self.connect lines where the streamer FIFOs get connected to the ZeroMQ sinks. If I comment out the connections to the ZeroMQ sinks, the application appears to run fine. I tried connecting the FIFOs to UDP sinks and null sinks and still get the same segfault. I have built uhd, gnuradio and gr-ettus all from source and cross compiled for the E310. I am using the Release 4 image and uhd was built from the rfnoc-devel branch. Commit ID is gec9138eb. Here is the log:
root@ettus-e3xx-sg1:~# python rfnoc_fosphor_network_usrp.py [INFO] [UHDlinux; GNU C++ version 4.9.2; Boost_105700; UHD_4.0.0.rfnoc-devel-409-gec9138eb] [INFO] [E300] Loading FPGA image: /home/root/localinstall/usr/share/uhd/images/usrp_e310_fpga.bit... [INFO] [E300] FPGA image loaded [INFO] [E300] Initializing core control (global registers)... [INFO] [E300] Performing register loopback test... [INFO] [E300] Register loopback test passed [INFO] [RFNOC RADIO] Register loopback test passed [INFO] [RFNOC RADIO] Register loopback test passed [WARNING] [RFNOC] [0/fosphor_0] defines 2 input buffer sizes, but 1 input ports [INFO] [AD936X] Performing CODEC loopback test... [INFO] [AD936X] CODEC loopback test passed [INFO] [AD936X] Performing CODEC loopback test... [INFO] [AD936X] CODEC loopback test passed [INFO] [CORES] Performing timer loopback test... [INFO] [CORES] Timer loopback test passed [INFO] [CORES] Performing timer loopback test... [INFO] [CORES] Timer loopback test passed Segmentation fault I also noticed that I am unable to run the rx_samples_to_file application. It seems like the FPGA gets loaded up correctly but exits immediately (I have read up on the fpga_idle image error so I'm not worried about that piece): root@ettus-e3xx-sg1:~/localinstall/usr/lib/uhd/examples# ./rx_samples_to_file --freq 100e6 --gain 0 --ant TX/RX --rate 1e6 --null Creating the usrp device with: ... [INFO] [UHDlinux; GNU C++ version 4.9.2; Boost_105700; UHD_4.0.0.rfnoc-devel-409-gec9138eb] [INFO] [E300] Loading FPGA image: /home/root/localinstall/usr/share/uhd/images/usrp_e310_fpga.bit... [INFO] [E300] FPGA image loaded [INFO] [E300] Initializing core control (global registers)... [INFO] [E300] Performing register loopback test... [INFO] [E300] Register loopback test passed [INFO] [RFNOC RADIO] Register loopback test passed [INFO] [RFNOC RADIO] Register loopback test passed [WARNING] [RFNOC] [0/fosphor_0] defines 2 input buffer sizes, but 1 input ports [INFO] [AD936X] Performing CODEC loopback test... [INFO] [AD936X] CODEC loopback test passed [INFO] [AD936X] Performing CODEC loopback test... [INFO] [AD936X] CODEC loopback test passed [INFO] [CORES] Performing timer loopback test... [INFO] [CORES] Timer loopback test passed [INFO] [E300] Loading FPGA image: /home/root/localinstall/usr/share/uhd/images/usrp_e3xx_fpga_idle.bit... [INFO] [E300] FPGA image loaded [ERROR] [UHD] Exception caught in safe-call. in virtual ctrl_iface_impl::~ctrl_iface_impl() at /home/wgs/rfnoc/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:76 this->peek32(0); -> AssertionError: (sts >> 7) & 0x1 in typename T::sptr e300_transport::get_buff(double) [with T = uhd::transport::managed_send_buffer; typename T::sptr = boost::intrusive_ptr<uhd::transport::managed_send_buffer>] at /home/wgs/rfnoc/src/uhd/host/lib/usrp/e300/e300_fifo_config.cpp:257 I suspect these 2 issues are related. Any information or hints that anyone could provide would be greatly appreciated. Thanks in advance for your time! lb
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