Thank you! :D From: Nick Foster [mailto:bistrom...@gmail.com] Sent: Thursday, 12 April 2018 1:38 PM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] AD9361 in USRP B210
They are both necessary and serve completely separate and complementary functions. At this point you are best served by reading the documentation. Nick On Wed, Apr 11, 2018, 10:33 PM Yeo Jin Kuang Alvin (IA) <yjink...@dso.org.sg<mailto:yjink...@dso.org.sg>> wrote: Hi, Thank you! Btw will the FPGA image be ‘overlap’ after running the UHD software or they can both run concurrently? Thank you in advance! From: Nick Foster [mailto:bistrom...@gmail.com<mailto:bistrom...@gmail.com>] Sent: Thursday, 12 April 2018 1:28 PM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Subject: Re: [USRP-users] AD9361 in USRP B210 On Wed, Apr 11, 2018 at 10:15 PM Yeo Jin Kuang Alvin (IA) <yjink...@dso.org.sg<mailto:yjink...@dso.org.sg>> wrote: Hi, Sorry I am very new to all these, do you mean that I have to download visual studio to compile all the UHD .cpp and run them for the UHD commands? No, I mean that you can probably just get away with using UHD as-is with a program you write (either in Python or C++) invoking a UHD device and configuring it. There are many examples included in uhd/host/examples. If you are lucky you might even get away with using one of the example programs without modification, but I doubt it. And for the FPGA image you talking about, is it the .bit file that is generated in the IMPACT? Yes. You have a long learning curve ahead of you. It's a good idea at this point to simply install UHD and get started using the B210 with some of the UHD examples to see how it works in practice. Nick Thank you in advance! From: Nick Foster [mailto:bistrom...@gmail.com<mailto:bistrom...@gmail.com>] Sent: Thursday, 12 April 2018 12:04 PM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Subject: Re: [USRP-users] AD9361 in USRP B210 The best option is probably to use existing UHD commands to set the gain, frequency, master clock rate, etc., while modifying the image to generate the transmit signal in the FPGA rather than in the host. Nick On Wed, Apr 11, 2018 at 6:41 PM Yeo Jin Kuang Alvin (IA) <yjink...@dso.org.sg<mailto:yjink...@dso.org.sg>> wrote: Hi, I have the FPGA source code using Xilinx ISE 14.7, I want to output a signal out that is generated from the FPGA, however I suppose I have to control the AD9361 to get an output out to transmit unless I am wrong. Thanks in advance! From: Nick Foster [mailto:bistrom...@gmail.com<mailto:bistrom...@gmail.com>] Sent: Thursday, 12 April 2018 9:39 AM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Subject: Re: [USRP-users] AD9361 in USRP B210 What exactly do you want to do? On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hi all, How do we set up the Ad9361_driver and ad9361 controls in the uhd/host/lib/usrp/common file for Ubuntu? What are the steps and prerequisites for this? Thank you in advance! _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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