Hi,
It seems that the minimum master_clock_rate for the B200 is fixed to 5
MHz in UHD :
static uhd::meta_range_t get_clock_rate_range(void)
{
//return uhd::meta_range_t(220e3, 61.44e6);
return uhd::meta_range_t(5e6,
ad9361_device_t::AD9361_MAX_CLOCK_RATE); //5 MHz DCM low end
}
And according to Xilinx specs, 5M is indeed the minimum for the DCM.
But I don't see anywhere in the fpga design a DCM being fed by that
clock line ...
Commit in question that set that limit was written by Josh Blum in 2013 :
commit 9c3fd671810abf0d39d7baa78073b90b95d9b5bc
Author: Josh Blum <[email protected]>
Date: Fri Aug 16 10:49:03 2013 -0700
b200: lower clock rate is 5MHz due to DCM
And looking a bit further I think that limit might be obsoleted by :
commit 450ab28c00e043123d81ecc70625027f59979f74
Author: Ian Buckley <[email protected]>
Date: Mon May 18 14:38:42 2015 -0700
B200: Brand new I/O design for B2x0 with no DCM. Should fix
issues: #754, #757, #734
Cheers,
Sylvain
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