Dear Ishai, I use the rfnocmodtool to work on the X310 USRP and I have 2 questions: > > 1. When I create a new block, can I define the code to be vhdl file > instead of Verilog file? > At this moment the tool does not have this option, but I see how this might result useful. I will upstream this and probably add this feature.
> 2. The second question is how to insert existing vhdl file to new > block that I create with rfnocmodtool. In case that I cannot open a new > vhdl file by rfnocmodtool, the only way that I think to do it, convert the > vhdl to Verilog file and to insert the content to the new block. Can > someone have another advice maybe? > > You can write your own modules in VHDL and then instantiate them into the noc_block_* directly. Functionality-wise, there is no need for you to translate the code unless you want to modify a large portion of it and you only intend to do this in VHDL. See the addsub module, for example, which can be written in VHDL[1] or Verilog[2]. The VHDL module can be then instantiated without the need of translation [3]. Cheers, - Nicolas [1] https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/addsub.vhd [2] https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/addsub.v [3] https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/noc_block_addsub.v#L94
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