Hi Anisha, There's a quick gotcha here: the "no_reload_fpga" flag also skips programming the FPGA when *starting* the program.
You should try programming the FPGA manually before running with "no_reload_fpga": `cat imagename.bit > /dev/xdevcfg` Cheers, EJ On Wed, Jun 13, 2018 at 10:24 AM Anisha Gorur via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > > Is there a way to run the e310 without loading the idle image after > completion? I saw from here: > http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2016-September/021984.html > that there is a flag you can pass called "no_reload_fpga", however, when I > try uhd_usrp_probe --args=no_reload_fpga, I receive the error > "RuntimeError: [ad9361_device_t] BBPLL not locked" almost immediately. > > Thanks, > > Anisha > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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