Hello all, Last week I posted a question, on how I could confirm that a custom RFNoC signal generator (piloted from a UHD API) functioned as intended. I received the tip to probe my block using the Vivado ILA. A great idea, because I did not know this existed (I am quite new in FPGA design) and it is a useful tool.
Now, I was able to confirm that my custom block is functioning as intended by placing an ILA internal to it. However, no actual samples are ever generated due to a design choice I made; sample generation is only triggered when the block receives a tready signal from a downstream block. In this case a DUC block. In other words, the block stays dormant, waiting to receive a trigger. That leaves me with the question why it never receives this signal. Could someone explain to me at what point a DUC block will assert its tready signal? I was under the impression that as soon as I connected the blocks (using uhd::rfnoc::graph::connect()) as follows: SIGGEN --> DUC --> Radio, the DUC and Radio blocks would be asserting their ready samples directly after. But apparently this is not the case. Thank you for your replies, Koen
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