I've also used axi_round_and_clip successfully.

I did find an edge case where part of the logic is incorrectly removed if
the WIDTH_OUT == CLIP_BITS. This was (very recently) updated:
https://github.com/EttusResearch/fpga/commit/454b17c501d333b06831ae535b6e60ba86d850af

I'd be curious to see if this particular scenario applies to you.

EJ

On Fri, Aug 31, 2018, 6:19 PM Nick Foster via USRP-users <
[email protected]> wrote:

> I've successfully used axi_round_and_clip in a number of designs and it
> seems to simulate fine for me. Xsim or vsim? How is it being instantiated?
> What weird internal simulation issues are you seeing?
>
> Nick
>
> On Fri, Aug 31, 2018 at 2:58 PM Andrew Danowitz via USRP-users <
> [email protected]> wrote:
>
>> When I try to use axi_round_and_clip in my design, simulation won't run
>> and has weird internal simulation issues. If I build it into an rfnoc
>> image, the flow graph doesn't return any data. Has anyone else run into
>> this?
>>
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