to be a little more specific: The baseband data rate of the FPGA / AD9361 interface limits the interface to a **cumulative** 61.44 in RX. So, no, that modification is not possible.
Best regards, Marcus M On Sun, 2018-09-09 at 13:37 -0700, Neel Pandeya via USRP-users wrote: > Hello Chintan: > > Yes, on the B210, in 1x1 mode, the maximum sampling rate is 61.44 > Msps, and in 2x2 mode, the maximum sampling rate is 30.72 Msps. > > The tweak/modification that you mention has not been implemented for > the B210. > > --Neel Pandeya > > > > > On 9 September 2018 at 13:20, Chintan Patel via USRP-users <usrp-user > [email protected]> wrote: > > Hi Marcus, > > > > Thanks for the clarification. So the max rate for two channels on > > the B210 is 30.72Msps, right? Reading the 9361 manual, it seems > > that if one wants to operate in RX-only (dual-port half-duplex) > > mode, the 61.44Msps rate might be achievable (at the expense of no > > TX). Any idea if this modification has been tried out on the B210? > > It would be an invasive change since the AD9361 digital interface > > in the FPGA would need tweaks, but any thoughts on if it was > > theoretically possible or not. > > > > Chintan > > > > > > On Sun, Sep 9, 2018 at 11:33 AM Marcus D. Leech via USRP-users <usr > > [email protected]> wrote: > > > On 09/09/2018 11:21 AM, Chintan Patel via USRP-users wrote: > > > > Hi, > > > > > > > > Two questions on the B210. > > > > > > > > 1. Generally speaking, are there are known issues transporting > > > two RX > > > > channels at 61.44Msps over USB 3.0 on the B210. I know from a > > > > theoretical standpoint, the 5Gbps capacity of USB 3.0 has > > > enough > > > > capacity to transport the dual-channel 16-bits i/q @ 61.44Msps. > > > I also > > > > know that whether the host can keep up with this throughput > > > depends on > > > > host configuration, load-balancing etc., but wanted to get a > > > general > > > > sense of which bucket it falls under: a) i > > > > quite-typical-and-routine-scenario, b) > > > > possible-but-in-a-particular-context, or c) pushing-the- > > > capabilities > > > > > > > > 2. Taking this thought a bit further - (our application needs > > > 4 > > > > channels), if we had a powerful dedicated host machine, how > > > > feasible/unrealistic is to to have a configuration where the > > > host is > > > > connected to two B210, via separate USB 3.0s and ingesting 4 > > > channels > > > > worth of RX data at 61.44Msps. From a UHD driver standpoint, I > > > am > > > > assuming this would just entail interfacing with two separate > > > > instances of streamers, but is there any pit-fall in the > > > single > > > > host-to-two-B210 approach? > > > > > > > > Thanks, > > > > Chintan > > > > > > > It's not a driver or host-beefiness issue with B210. It's the > > > way the > > > data clocks work on the AD9361 chip, and the interface to the > > > FPGA. > > > > > > There's simply no way to make the AD9361 chip move two channels > > > of data > > > out of itself (or, into itself) at the maximum data rate. > > > > > > > > > > > > _______________________________________________ > > > USRP-users mailing list > > > [email protected] > > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.co > > > m > > > > _______________________________________________ > > USRP-users mailing list > > [email protected] > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > > _______________________________________________ > USRP-users mailing list > [email protected] > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com _______________________________________________ USRP-users mailing list [email protected] http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
