Hi all, After updating fpga source to most recent master branch, I noticed that rfnoc blocks, which uses HLS generated IP cores, are no longer synthesizing with the project. Furthermore, viv_hls_ip_builder is not starting at all. I think that the reason of this problem is missing HLS targets in main x300 makefile (Makefile.x300.inc). Could someone confirm this issue / propose solution?
Error from building example provided by Ettus (addsub_hls): ERROR: [Synth 8-439] module 'addsub_hls' not found [/workarea/fpga/usrp3/lib/rfnoc/noc_block_addsub.v:88] ERROR: [Synth 8-285] failed synthesizing module 'noc_block_addsub' [/workarea/fpga/usrp3/lib/rfnoc/noc_block_addsub.v:8] ERROR: [Synth 8-285] failed synthesizing module 'x300_core' [/workarea/fpga/usrp3/top/x300/x300_core.v:8] ERROR: [Synth 8-285] failed synthesizing module 'x300' [/workarea/fpga/usrp3/top/x300/x300.v:20] ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details [00:03:07] Current task: Synthesis +++ Current Phase: Starting [00:03:07] Current task: Synthesis +++ Current Phase: Finished [00:03:07] Process terminated. Status: Failure -- Best regards Arnika
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