Hi Brian,

thanks! Quick update first: raised the CMakeLists omission internally,
should be fixed soon, far as I can tell.

Best regards,
Marcus
On Mon, 2018-09-24 at 14:52 -0400, Brian Padalino via USRP-users wrote:
> I noticed that the dma_fifo_block_ctrl.hpp file isn't included in the
> installation of UHD as of current master:
> 
>   
> https://github.com/EttusResearch/uhd/blob/6af6ac32c30d2dc0efa6eab61e4a3920649e3e62/host/include/uhd/rfnoc/CMakeLists.txt
> 
> It seems like this is just a simple oversight, so I modified it
> locally.  I've been running doing some latency experiments and
> modifying the size of the DMA FIFO using the resize() method:
> 
>   
> https://github.com/EttusResearch/uhd/blob/6af6ac32c30d2dc0efa6eab61e4a3920649e3e62/host/lib/rfnoc/dma_fifo_block_ctrl_impl.cpp#L65
> 
> And it seems there's a bit of a restriction on the sizing associated
> with the FIFO:
> 
>   
> https://github.com/EttusResearch/uhd/blob/6af6ac32c30d2dc0efa6eab61e4a3920649e3e62/host/lib/usrp/cores/dma_fifo_core_3000.cpp#L263
> 
> I see it currently says that the FIFO needs to be >8k, and it has to
> be a power of 2.  If either of those criteria fails, an exception is
> thrown.
> 
> A few requests:
> 
> (1) Can you not throw an exception, but print a warning and resolve
> the criteria?  For example, if I ask for < 8k, up it to 8k and print
> a warning it's been upped.  If I ask for a non-power of 2, can you
> print a warning and up to to the next supported power of 2?  Think of
> this like a request for a sample rate - if you can't get the exact
> one, you get what's close and the user can query the actual value?
> 
> (2) Speaking of powers of 2, why is this a requirement?  Can it be
> any value that is a multiple of a 4k page boundary?  Is there
> something inside the FPGA logic that doesn't allow this to happen? 
> Powers of 2 can be a large buffer size changes.
> 
> Thanks,
> Brian
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