Hi Daniel, Sad to hear that! By the way, I forgot to mention another important rate I need, 3 MHz, that also has an integer relationship to 120 MHz... Perhaps I'd like to make a formal feature request for 120 MHz master clock?? It strikes me as odd that so many of the "whole number" MHz sample rates are neglected on the n3xx series by default-- it's often the case that I'll want to interact with other hardware with baud rates at, say, 2 MHz or 10 MHz or something, but I just don't have the fpga-based fractional conversions onhand right now...
I'm certainly not afraid of nontrivial changes, so if the AD9371 supports a clock rate that can give me these derived sample rates, I really see this as the best solution since other platforms can already achieve these rates without extra user-space processing requirements. However, if needed, potentially a "quick and dirty" approach might be to make an rfnoc fractional resampler that combines a DUC and DDC into one "ce", with a block controller to calculate the magical conversions... It's not an optimal solution but it might do the trick here. Anyone else interested in such an fpga-based fractional resampler? EJ On Wed, Oct 17, 2018, 1:52 PM Daniel Jepson via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi EJ, > > The fundamental limitation comes from the AD9371. Although the datasheet > specifies a wide reference clock input range, there are only certain > supported rates within the public side of their API (at least that I'm > aware of). These include the rates you mentioned from the KB. > > Assuming the AD9371 allows it, adding a new MCR is not trivial and would > require a good deal of work across hardware, FPGA code, and MPM. The > fractional resampler sounds like a much better path forward, albeit > difficult right now. > > Hopefully that explains some of the background on the chosen MCRs. Sorry > it wasn't exactly what you were hoping for! > > -Daniel > > On Wed, Oct 17, 2018 at 10:50 AM EJ Kreinar via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi all, >> >> I'm working on an FPGA application on the n310/n300, and I'm bumping into >> a limitation of the master_clock_rate selection.... I'd like to be able to >> use sample rates in the FPGA of 2 MHz, 4 MHz, and 10 MHz, but none of these >> values are integer multiples of the supported rates (122.88e6, 125e6, >> 153.6e6 -- from here: >> https://kb.ettus.com/N300/N310_Getting_Started_Guides#Supported_Sample_Rates). >> This causes a problem in the FPGA since I would need a fractional >> resampler, which I dont currently have, unfortunately. >> >> What's the fundamental limitation of these master clock rates? I would >> have assumed that the AD9371-based architecture would have resulted in a >> wider variety of plausible clock rates, similar to the AD9361 on the E310. >> I havent found these limits yet in the software or FPGA, so any pointers >> where to look would be appreciated. >> >> As a follow up question, how feasible would it be to add a master clock >> rate of 120 MHz?? Any ideas where to make these changes? This would answer >> the mail for my sample rates of interest right now. >> >> Thanks! >> EJ >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > > > -- > > Daniel Jepson > > Digital Hardware Engineer > > National Instruments > > > > O: +1.512.683.6163 > > daniel.jep...@ni.com > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > On Wed, Oct 17, 2018, 1:52 PM Daniel Jepson via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi EJ, > > The fundamental limitation comes from the AD9371. Although the datasheet > specifies a wide reference clock input range, there are only certain > supported rates within the public side of their API (at least that I'm > aware of). These include the rates you mentioned from the KB. > > Assuming the AD9371 allows it, adding a new MCR is not trivial and would > require a good deal of work across hardware, FPGA code, and MPM. The > fractional resampler sounds like a much better path forward, albeit > difficult right now. > > Hopefully that explains some of the background on the chosen MCRs. Sorry > it wasn't exactly what you were hoping for! > > -Daniel > > On Wed, Oct 17, 2018 at 10:50 AM EJ Kreinar via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi all, >> >> I'm working on an FPGA application on the n310/n300, and I'm bumping into >> a limitation of the master_clock_rate selection.... I'd like to be able to >> use sample rates in the FPGA of 2 MHz, 4 MHz, and 10 MHz, but none of these >> values are integer multiples of the supported rates (122.88e6, 125e6, >> 153.6e6 -- from here: >> https://kb.ettus.com/N300/N310_Getting_Started_Guides#Supported_Sample_Rates). >> This causes a problem in the FPGA since I would need a fractional >> resampler, which I dont currently have, unfortunately. >> >> What's the fundamental limitation of these master clock rates? I would >> have assumed that the AD9371-based architecture would have resulted in a >> wider variety of plausible clock rates, similar to the AD9361 on the E310. >> I havent found these limits yet in the software or FPGA, so any pointers >> where to look would be appreciated. >> >> As a follow up question, how feasible would it be to add a master clock >> rate of 120 MHz?? Any ideas where to make these changes? This would answer >> the mail for my sample rates of interest right now. >> >> Thanks! >> EJ >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > > > -- > > Daniel Jepson > > Digital Hardware Engineer > > National Instruments > > > > O: +1.512.683.6163 > > daniel.jep...@ni.com > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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