On 10/25/2018 11:33 AM, Christopher Willuweit wrote:
Hi,
thanks for the reply. The offset is constant, i tested for maybe an
hour using different flow graphs.I also expected absolute error of
maybe 20ppm, jitter and varying frequency changes but not a constant
offset between the two frontends. Can you reproduce this behaviour?
I only have 1 UBX in my lab.
Perhaps someone in Ettus R&D can reproduce the results, or comment on
why this is to be expected.
I'll note that the residual frequency error we're talking about is only
5PPB, but in the case at hand, it really should be zero.
------------------------------------------------------------------------
*Von:* USRP-users <usrp-users-boun...@lists.ettus.com> im Auftrag von
Marcus D. Leech via USRP-users <usrp-users@lists.ettus.com>
*Gesendet:* Donnerstag, 25. Oktober 2018 17:14:57
*An:* usrp-users@lists.ettus.com
*Betreff:* Re: [USRP-users] LO-Offset between two UBX Daugtherboards
On 10/25/2018 04:16 AM, Christopher Willuweit via USRP-users wrote:
Hi all,
I want to use a single X310 w/ two UBX-160-Daughterboards for a
simple transmission setup. You can find the GRC-Flowgraph and a
screenshot of the result attached in this mail. I'm experiencing an
LO-Offset of ~12Hz and just wanted to know if this is normal. As far
as i can tell from schematics, the PLLs in the daughterboard have
reference clocks generated by a clock distribution chip in the X310.
Since the wires are of matched length i would assume that they can be
used frequency and phase synchronized. Did i get something wrong with
my settings? On the ettus website i can only find information for
phase coherent setups using multiple USRPs. For a start a frequency
synchronized setup would be sufficient for my application, phase does
not matter.
Currently i'm using UHD version 3.14.0.HEAD-31-g98057752
kind regards and thanks!
Christopher Willuweit
I have to admit, this is a bit odd.
Does the frequency error change over time?
With both UBX getting the same clock, and the same programming, the
residual mutual frequency error should be zero. The absolute frequency
error, of course, could be much larger, but it will (should) be the
same for both UBX -- same PLLs, same refclock, same programming.
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