Hello all,
I am trying to understand what is going on while receiving RF data in
USRP E310. I am using gnuradio in programming of USRP E310.
I investigated AD9361 chip and the baseband data rate of AD9361 is
maximum of 61.44MHz. So this is equal to master clock rate as i
understood. For example, if i set the sample rate of USRP source block
in gnuradio to 10MHz, What will happen?
Q1.
My Approach 1. There are several filters and decimators in AD9361. So,
in AD9361 the ADC samples at rate of for example at 100MHz and using
decimators in AD9361, the baseband data rate of 10MHz is obtained. Is
this what happened ? (In this case FPGA blocks (DDC, DDU and radio) are
not used)
or,
My Approach 2. The baseband rate of AD9361 is set to for example 40MHz
using decimators and filters and data is passed to FPGA. In FPGA, using
the DDC the rate of data is reduced to 10MHz. Is this what happened?
Q2.
Actually, i am confused in FPGA part of receiver. Normally, without
using the RFNoC do the DDC and DDU blocks in FPGA are used to obtain
desirable sample rate? or When i use the RFNoC programming in gnuradio,
i can activate them. Relating to RFNoC and FPGA radio, DDC, DDU blocks,
can you review my approaches?
My questions are related to each other. FPGA and RFNoC part is big
question mark in my mind. If you give some information about FPGA part
with or without RFNoC, after answering my questions, i will appreciate.
Best regards.
Ramazan
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