Hi Marcus,
I have compiled proper image(fft, ddc, keep 1 to n) and did what you
said. Now, it looks better, i am getting very little overruns sometimes.
I have another question. I am sorry if question is not related with this
topic.
I changed my flowgraph to this:
RFNOC_radio --(56MHz)> RFNOC_FFT -> RFNOC_DDC --(2MHz)> complexToMag ->
Log10 -> FileSink
I want to get wifi samples from E310 which has 56 MHz analog BW. So, i
can get wifi samples from FPGA but not in CPU. I want to see wifi
samples on frequency spectrum on CPU. So, i thought that i can get 56
MHz signal on FPGA and get FFT. After FFT, downsample FFT results and
push FFT samples to CPU as 1-5Ms/s. But when i looked my signal on CPU,
its so distorted.
Q1. So, do you know any method to minimize signal distortion while
downsampling in frequency domain? or How can i get wifi signal frequency
spectrum in E310 ?
Q2. When i try compiling FPGA image with 4 blocks, it gives "Placer
could not place all instances" error. But in guide, it says user can put
up to 6 blocks. Why it give that error after 3 blocks?
Best regards.
On 9.02.2019 17:11, Marcus D. Leech wrote:
On 02/09/2019 07:05 AM, Ramazan Çetin via USRP-users wrote:
Hello all,
I want to get fft of 50Ms/s signal and after fft using DDC i will
pass the samples with 1-5Ms/s to ARM processor.
I have compiled an FPGA image with FFT, DDC and FIFO.
| | _____________________________________________________
| | /
| | | RFNoC blocks on this device:
| | |
| | | * Radio_0
| | | * DDC_0
| | | * FFT_0
| | | * FIFO_0
I have a gnuradio flowgraph (It is attached);
Radio -> strToVector -> FIFO -> FFT -> vectorToStr -> CompToMag ->
NullSink
When i used master clock rate 1M, there is no overruns. After 1M for
example (1.5M) i am getting overruns.
[INFO] [E300] Performing register loopback test...
[INFO] [E300] Register loopback test passed
[INFO] [0/Radio_0] Initializing block control (NOC ID:
0x12AD100000000000)
[INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0000000000000)
[WARNING] [RFNOC] Can't find a block controller for key FFT, using
default block controller!
[INFO] [0/FFT_0] Initializing block control (NOC ID: 0xFF70000000000000)
[INFO] [0/FIFO_0] Initializing block control (NOC ID:
0xF1F0000000000000)
[WARNING] [RFNOC] Assuming max packet size for 0/FIFO_0
Press Enter to quit: overrun on chan 0O
overrun on chan 0
Ooverrun on chan 0
Ooverrun on chan 0
Ooverrun on chan 0
Ooverrun on chan 0
Ooverrun on chan O0
overrun on chan 0
So, why is this happening? I thought i am handling data in FPGA so i
can get FFT of 50Ms/s signal. I just need to reduce sampling rate
when i pass the samples to ARM processor. What is wrong with my setup?
Thank you. Best regards.
Ramazan
Notice how there aren't strToVector blocks in the list of RFNOC
blocks, nor complex-to-mag. That means the samples are visiting the CPU
at high rate.
The flow would be:
Radio-->FFT--->IIR_FILTER-->KEEP_1_IN_N--->then do the complex-to-mag
on the host.
However, you're missing RFNoC blocks for the IIR filter and KEEP_1_IN_N
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