Hi Mark-Jan,

Thanks for your response.

On 03/05/2019 00:02, Mark-Jan Bastian wrote:
> For more in-depth USB debugging, there are external USB 2.0 and 3.x 
> hardware bus analysers available, for example from the swiss company
> ellisys.com.

I have experience in USB protocol analysis from a previous job, and know
the Ellisys tools among others. As a consequence, I have an idea about
what effort it implies to look at the problem from that angle (one could
call this a "bottom-up approach"), and I won't go that way.


> Some things can be very subtle, for example this (quite amazing)
> 2013 ethernet PHY bug:
> https://www.theregister.co.uk/2013/02/06/packet_of_death_intel_ethernet/
> Very tough engineering by the affacted customer, who made it reproducable
> and fixed by a simple EEprom update from the vendor.

Interesting story, but I hope it is not a parallel to my situation, and
that a simpler approach will fix it.


> Pure theory: What if this intermittent issue would be an issue with a 
> certain sequence of packetlengths, some of them on the boundary of the 
> maximum size for that endpoint and endpointtype, that are not handled 
> properly at one or both sides, causing a glitch/retransmission/faillure, 
> resulting in the application-level visible underruns ?
> How would you measure that ? How could you optimize the packetlengths 
> so that the issue is quicker to reproduce ? Or avoid the issue by
> anticipating and avoiding such packetsequences ?

It's a possible hypothesis, but I don't see how to test it easily.


>> Could CPU frequency scaling lead to interruptions?
> 
> It would leave that off [...]

I'd love to, but it's not clear to me how to achieve that nowadays with
the intel_pstate driver:

https://www.kernel.org/doc/html/v4.12/admin-guide/pm/intel_pstate.html

It's probably not even possible anymore given that the cpu and voltage
scaling responsiblity got moved into the processor itself.

mpb

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