Hi, You are building an image with 1 x DDC and 7 x FIFO RFNoC blocks due to the arg "--fill-with-fifos". Remove that arg and your utilization should be significantly lower.
Jonathon On Mon, Jul 1, 2019 at 1:42 AM Andrew Thommesen via USRP-users < [email protected]> wrote: > Hi, > > According to this link (https://kb.ettus.com/X300/X310) the baselink > RFNoC X310 image should use <25% of the available LUTs. However, my build > uses more than 50% with a single DDC using the same UHD release: > > ./uhd_image_builder.py ddc -d x310 -t X310_RFNOC_HG -m 8 --fill-with-fifos. > > The DDC should not require >25% of the available LUTS, so am i missing > something? Should I be using an alternative to the X310_RFNOC_HG base > image to achieve this utilisation. > I really need that 25% of LUTS for my design so any guidance would be > gratefully received. > > Thanks, > > Andy > X300/X310 - Ettus Knowledge Base <https://kb.ettus.com/X300/X310> > Device Overview. The Ettus Research USRP X310 is a high-performance, > scalable software defined radio (SDR) platform for designing and deploying > next generation wireless communications systems. > kb.ettus.com > > > Sent from Outlook <http://aka.ms/weboutlook> > _______________________________________________ > USRP-users mailing list > [email protected] > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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