Hi, I did a noc_block with 2 input and 1 out. May be my solution is not the best, but it works.
My block receive two inputs, perform some elaboration on both inputs, and then merge the results in only on output stream. My start point was the noc_block_addsub, and I had simply tied to 0 the valid out for the second output. Regards Paolo On 02/07/19 15:15, Mitch Davis via USRP-users wrote: > Has anyone successfully created a 2-input, 1-output RFNoC block that > they could share, or at least help me figure out what I'm doing > incorrectly? > > I had set out to create a 2-input, 1-output RFNoC block: Complex > Multiply. There's already a 'cmul' module in the uhd-fpga source, all > it needed was a proper RFNoC wrapper. > > I reviewed the source of the addsub block, as it has two inputs. > However, its a little odd in its implementation as it doesn't follow > the design pattern using an AXI wrapper between the the RFNoC shell and > the module IP. It uses its own chdr deframer (which is what > axi_wrapper seems like it should do instead). > > I had also found this list post from 2017: > http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2017-June/053156.html > > There didn't appear to be any published resolution on that thread. > > It turns out, finding information on 2-input, 1-output blocks is a bit > of a challenge, some other relevant posts: > http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2018-January/055504.html > > I had also found this post that featured some example code and some > discussion about a "combiner" block. It's very similar to what I > needed to do, but different arithmetic required: > http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2017-October/054654.html > > Another list post about 2-in 1-out, but no clear resolution (other than > physical limitations): > http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2017-September/054460.html > > > So, armed with some information I followed > https://kb.ettus.com/Getting_Started_with_RFNoC_Development#Starting_a_custom_RFNoC_block_using_RFNoC_Modtool > > and created a module. > > The skeleton loopback code worked just fine with the testbench. I then > modified the testbench similar to the addsub testbench and added code > for the cmul IP, and modified the noc block and noc shell settings to > support 2 inputs, 1 output. Running that testbench resulted in an > unexpected result: it seemed that the second AXI stream wasn't > receiving data from the testbench. > > I figured my best course of action then was to use Andy's combiner > block, because it allegedly runs in a testbench. If it runs with my > testbench, then I have some verilog problems to debug. However, I was > unable to get Andy's combiner working in my testbench. His code has > been renamed "multiplycomplex" for the sake of in-situ testing with my > multiply-complex testbench. This leads me to believe I'm doing > something wrong with how I'm presenting the test vectors in the > testbench. > > Thanks! > > -Mitch > > > > > > _______________________________________________ > USRP-users mailing list > [email protected] > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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