Hi Scott, The CORDIC Xilinx IP is breaking timing. The CORDIC's bit width could be better optimized, but changing it would require editing of other parts of the code too.
One simple thing you could try is hand editing fpga/usrp3/top/x300/rfnoc_ce_auto_inst_x310.v and changing noc_block_schmidl_cox's input from ".ce_clk(ce_clk)," to ".ce_clk(bus_clk),". Note that the file is overwritten when running uhd_image_builder, so you'll need to run the FPGA build Makefile manually (i.e. make X310_HG_RFNOC). If you are still failing timing using bus_clk, you can also try bus_clk_div2. Jonathon On Thu, Jul 18, 2019 at 9:34 PM Scott Mullin <[email protected]> wrote: > Jonathan, > Thanks for the heads up on this block.Full disclosure, I am fairly new to > this so I am not sure how to tell. Here are the build.rpt and timing > reports from the build I did this morning. > > Hope that helps. > > Scott > > On Wed, Jul 17, 2019 at 11:50 PM Jonathon Pendlum < > [email protected]> wrote: > >> Hi Scott, >> >> What paths are failing timing? Also, the Schmidl Cox block has some >> design issues that need fixed before it can be useful again. If I remember >> correctly, I think there is an issue with the peak detection logic. >> >> Jonathon >> >> On Wed, Jul 17, 2019 at 2:28 AM Scott Mullin via USRP-users < >> [email protected]> wrote: >> >>> Hello, >>> >>> I am trying to use the schmidl_cox noc block but when I build an fpga >>> image for an x310 with uhd_image_builder I get a timing error. I have >>> tried building an fpga image with only one CE, the scmidl_cox noc block, >>> and it still gives me a timing error, so its not due to resource >>> utilization, which is when I typically get a timing error. >>> >>> Has anyone else had this issue? Any help would be appreciated. >>> >>> -- >>> Scott Mullin >>> >>> _______________________________________________ >>> USRP-users mailing list >>> [email protected] >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >> > > -- > Scott Mullin > University of Notre Dame > Engineering and Design Core Facility > 204D Nieuwland Science Hall > University of Notre Dame > IN 46556 >
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