I havent seen anything too egregious inspecting the files you sent. A few debugging ideas... - Are you able to run the simulation testbench correctly for noc_block_fmdemod? - I didnt see your file that corresponds with the ip/Makefile.inc ( https://github.com/ejk43/rfnoc-ootexample/blob/master/rfnoc/ip/Makefile.inc). Do you have that file in your tree, and does it correctly point to the IP you're trying to build?
If your code is on github link I could take a look that way -- might be easier to diagnose. EJ On Tue, Jul 23, 2019 at 7:53 AM Kirsten S Leong <leo...@purdue.edu> wrote: > I've attached the makefiles of the IPs and the other subdirectories in the > rfnoc folder. > > > Thanks, > > Kirsten > ------------------------------ > *From:* EJ Kreinar <ejkrei...@gmail.com> > *Sent:* Monday, July 22, 2019 6:36:27 PM > *To:* Kirsten S Leong <leo...@purdue.edu> > *Subject:* Re: RFNoC OOT Issues > > Okay sounds good. > > Rfnoc devel branch should be fine, but it's now getting a bit old. The > most updated guidance I would recommend is to use one of their tagged > branches, say v3.13.x.x or v3.14.x.x. The software needs a cmake compile > flag "-DENABLE_RFNOC 1" but that's a bit downstream... > > The most likely scenario here is that the makefiles for building the IP > aren't quite right. Can you copy or attach the makefiles from the ip folder > and subdirectories? > > Also, building the IP inside the fpga folder is intended behavior-- it's > all generated to retarget each part you build for. > > EJ > > On Mon, Jul 22, 2019, 9:19 PM Kirsten S Leong <leo...@purdue.edu> wrote: > > Yes, I emailed the mailing list. I'll shift over there once I have access > to my work email. > > I pulled from the rfnoc-devel branch and the data width converter is in > the ip folder of my OOT module. > > Thanks, > Kirsten > ------------------------------ > *From:* EJ Kreinar <ejkrei...@gmail.com> > *Sent:* Monday, July 22, 2019 5:33:02 PM > *To:* Kirsten S Leong <leo...@purdue.edu> > *Subject:* Re: RFNoC OOT Issues > > Hi Kirsten, > > Not sure what you mean by the usrp users site? You should be able to just > email the mailing list at usrp-users@lists.ettus.com > > Anyway, first what version of uhd-fpga are you using? > > Also, is this ip from your OOT module? > > Feel free to send to the usrp-users mailing list too if you'd like to chat > there. > > Best regards, > Ej > > > > On Mon, Jul 22, 2019, 4:52 PM Kirsten S Leong <leo...@purdue.edu> wrote: > > Hello, > > > I first submitted a post to the USRP-users site but it hasn't been > accepted for a week. It's my first time building an RFNoC image and was > running into issues on my custom OOT block which uses Xilinx IPs and a data > width converter. I modeled the Makefiles after the ones in your example > repository but I get the error: > > > make[1]:***No rule to make target > '/home/kleong/projects/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axis_dwidth_converter_32to64/axis_dwidth_converter_32to64.xci', > needed by 'bin'. Stop. > > make[1]: Leaving directory '/home/kleong/projects/fpga/usrp3/top/x300' > > Makefile:119: recipe for target 'X310_RFNOC_HG' failed > > make: *** [X310_RFNOC_HG] Error 2 > > > This occurs when I run the command ./uhd_image_builder.py fmdemod -t > X310_RFNOC_HG -d X310 -I /home/kleong/projects/rfnoc-fmdemod/rfnoc/ > --fill-with-fifos > > > The block can be successfully simulated, but I'm not sure why make file is > looking for the IPs in the fpga repository. > > > Thanks, > > Kirsten > > >
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