>From What I have observed t
I did some measurements at the oscilloscope but, from my observations the
214.86 Mhz clock and the 200 MHz clock are not synchronized. I might be wrong.
Then I also looked to the x300.v files.
It seems that the two clocks are deriving from two different clock branches
feeded by two inputs.
The 214 MHz (bus_clk) derived from the first branch.
The 200 MHz (radio_clk) derived from the second branch. But I don't see where
they are synchronized. From what I have observed only the branch 2 is sync to
the 10 MHz reference.
In any cases I am now using the radio_clk as my CE main clock and the system is
working as expected.
(See below for the branches)
Best Regards
Cherif
(from x300.v verilog file)
====branch 2 (radio_clk)
wire radio_clk_locked;
radio_clk_gen radio_clk_gen (
.clk_in1_p(FPGA_CLK_p), .clk_in1_n(FPGA_CLK_n),
.CLK_OUT1(radio_clk), .CLK_OUT2(radio_clk_2x), .CLK_OUT3(dac_dci_clk),
.RESET(sw_rst[2]), .LOCKED(radio_clk_locked));
.
====branch 1 (bus_clk)
IBUFG fpga_125MHz_clk_buf (
.I(FPGA_125MHz_CLK),
.O(fpga_clk125));
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___187.500______0.000______50.0_______85.263_____73.940
// CLK_OUT2___125.000______0.000______50.0_______91.831_____73.940
// CLK_OUT3____93.750______0.000______50.0_______96.813_____73.940
// CLK_OUT4___214.286______0.000______50.0_______83.210_____73.940
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________125.000____________0.010
localparam BUS_CLK_RATE = 32'd187500000;
wire ioport2_clk_unbuf;
bus_clk_gen bus_clk_gen (
.CLK_IN1(fpga_clk125),
.CLKFB_IN(ioport2_clk),
.CLK_OUT1(bus_clk),
.CLK_OUT2_UNBUF(/* unused */), //This exists to make the IP generate a
125MHz FB clock
.CLK_OUT3(bus_clk_div2), //bus_clk divided by 2. used by sc/zpu
.CLK_OUT4(ce_clk),
.CLKFB_OUT(ioport2_clk_unbuf),
.LOCKED(bus_clk_locked));
________________________________
From: Nick Foster <[email protected]>
Sent: Monday, August 5, 2019 10:39 PM
To: Cherif Diouf
Cc: [email protected]
Subject: Re: [USRP-users] 214 MHz ce_clk vs 200 MHz radio_clk, USRP X310
All synthesized clocks are synchronized to whatever reference is selected.
On Mon, Aug 5, 2019 at 1:03 PM Cherif Diouf
<[email protected]<mailto:[email protected]>> wrote:
Thanks Nick,
That's fine as explanation. I however need a HW clock synchronized to the 10
MHz external reference. I am using some local counters to run timely
operations. If not using the 200 MHz clock Is it possible to synchronize the
214 MHz clock to the 10 MHz external reference.
Best Regards
Cherif
________________________________
From: Nick Foster <[email protected]<mailto:[email protected]>>
Sent: Monday, August 5, 2019 6:33:37 PM
To: Cherif Diouf
Cc: [email protected]<mailto:[email protected]>
Subject: Re: [USRP-users] 214 MHz ce_clk vs 200 MHz radio_clk, USRP X310
The radio TX frontend backpressures upstream blocks. You don't have to worry
about providing samples at the frontend rate. There is no reason to use a
200MHz clock in your block.
Remember: if the frontend is operating at 200Msps, then the samples your block
is producing must assume a 200Msps sample rate. It doesn't matter at all that
the clock driving your block is 214MHz -- that only means that the logic is
operating a bit faster.
Nick
On Mon, Aug 5, 2019 at 8:58 AM Cherif Diouf via USRP-users
<[email protected]<mailto:[email protected]>> wrote:
________________________________
Hello guys,
I am working with the X310 USRP. I have developed customed RFNoC CEs running at
ce_clk which is no more 200 MHz but rather 214 MHz.
So my blocks are providing samples to the RF frontends at 214 MSps. Is that
right?
Then how the operation can be consistent when the sampling rate of the RF
frontends is still at 200MSps.
Is it possible to synchronize both the 214 MHz and the 200 MHz clocks to the
same 10 MHz external reference, or to use the 200 MHz reference clock as my HW
blocks main clock?
Best Regards
Cherif
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