Hello, I have been trying to build FPGA image for the RFNoC OFDM blocks - schmidl_cox, eq and ofdm_constellation demapper.
I have tried different combination of build with just schimdl_cox or eq or ofdm_constellation_demapper: 1) For eq build, I always got the following error: ERROR: [Opt 31-2] SRLC32E x300_core/inst_eq/inst_axi_wrapper/header_fifo/fifo_short/gen_srlc32e[64].srlc32e is missing a connection on D pin. 2) For schmidl_cox or ofdm_constellation_demapper, I got the following problem: ERROR: [Builder 0-0] The design did not satisfy timing constraints. (Implementation outputs were still generated) Can anyone help with these issues? Thanks, Huacheng
_______________________________________________ USRP-users mailing list [email protected] http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
