Hello Adnan, I'm currently not aware of anyone doing that.
However, since one of the typical applications of beefier FPGAs is math accelerators for linear algebra problems, it's more than likely someone did in fact implement an SVD before, and you might just need to connect it to a nocshell to make it work in RFNoC. There's a lot of interesting papers out there on SVD implementations for fixed point math on FPGAs, I think Drexel uni had some interesting stuff for SVD-based channel estimation for OFDM. I've not seen any code of them, though... So, from an algorithmic point of view, an SVD isn't too hard. IIRC, sequential algorithms can work in-place, and thus (for a m×n matrix, n>m) don't need more than n² space for intermediate and final result (+2m for index and scale storage if you want to pivot elegantly). Now, I've not ever implemented more than a C++ QR decomposition (which is the core algorithm for most EVD problems, which you typically householder-transform an SVD problem to), so I'm really not competent to comment on hardware implementations, but chances are you want to compute a lot of result values in parallel if you're doing it in the FPGA – because otherwise, you'd abhor doing much work in hardware (that being _hard_) in favor of doing it easier-to-debug and also free-to- have in the shape of LAPACK software. (Subtext message, more for future readers than for you: Evaluate whether something really should be done in hardware; it's not inherently better to do things in hardware.) But that parallelism might imply that in-place is not a feasible way of computing things, and your memory requirements might be much larger. Depending on the size of SVD you're planning to do, that might or might not be an issue. Best regards, Marcus On Fri, 2019-09-06 at 19:05 +0000, Quadri,Adnan via USRP-users wrote: > Hello, > > We are trying to perform singular vector decomposition. The idea is > to work on an RFNoC block that takes in summation of samples from the > Radio source and will perform SVD. > > Is anybody working on something similar? > Currently, the RFNoC OFDM synchronizer block has timing constraint > issues and can't be used to build FPGA image. > > Just asking around to get some suggestions/advice and idea if working > on that Verilog implementation of SVD is something doable and if > anybody tried anything similar. > > Thank you, > Adnan > > > _______________________________________________ > USRP-users mailing list > USRPemail@example.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com _______________________________________________ USRP-users mailing list USRPfirstname.lastname@example.org http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com