Hi Nate, I'm using UHD 3.14.0.1. I am not using DPDK. Regarding the tuning, I think I was not clear in my email. I have no trouble streaming to RAM disk using the standard Radio->DDC->host graph. I mentioned that I was running 2x50MS/s, but I can go up to 2x200MS/s with success. My issue is that after adding the DmaFIFO to the Rx chain, I got timeouts (i.e., I suppose that the flow stopped for some reason) when running the graph Radio->DDC->DmaFIFO->host. Even at 2x50MS/s.
So, my question is: why is this happening? What is wrong with my plan to insert the DmaFIFO in the Rx chain? What would possibly cause the streaming to terminate such that my recv() loop times out (even with a 5s timeout)? Rob On Fri, Sep 6, 2019 at 12:56 PM Ettus Research Support <[email protected]> wrote: > Hi Rob, > > What version of UHD are you using? > > 2x RX 50 MS/s streams should work without much issue with a fast enough > host, especially to a ram disk. > > Are you using DPDK? DPDK support for X3xx was recently added to UHD and > will reduce the overhead on the host side, which can help quite a bit. Some > anecdotal testing I've done with a N310, with the native UHD driver, to > stream 2 channels full duplex, the minimum cpu freq I was able to run > without any flow control errors was 3.8 GHz. Using DPDK, I was able to run > 2x2 @ 125 MS/s with my CPU cores locked at 1.5 GHz with no flow control > errors. Using DPDK, it's possible to stream 2x2 @ 200e6 on the X3xx with a > SRAM FPGA image (it's not possible to TX at full rate using the native > driver and DRAM based FPGA). > > You could try the few things listed here > https://kb.ettus.com/USRP_Host_Performance_Tuning_Tips_and_Tricks > > One other bit to add, I've been able to stream 1 RX channel @ 200 MS/s > straight to disk using a Intel 750 Series PCIe SSD until it was full (circa > UHD 3.10.x). To do that, I had to use a sc16 host side data format and also > use a XFS file system instead of EXT4. The host was a i7-4790k @ 4.4 GHz. I > would recommend NVMe SSD drives now as they support faster rates than that > PCIe SSD. > > > Regards, > Nate Temple > > On Fri, Sep 6, 2019 at 8:37 AM Rob Kossler via USRP-users < > [email protected]> wrote: > >> Hi, >> As part of an effort to improve capability to store incoming receive >> chain samples to files on my SSD without errors ('O' or 'D'), I decided to >> wire an X310 noc graph to include the DmaFIFO. My thought was that the >> DmaFIFO could better tolerate varying rates of sample consumption at the >> OS. >> >> Before trying this by streaming to a file on my SSD, I first ran a test >> which streamed to a RAM-based file (60 GB ram filesystem). I used an >> X310/UBX160 with the default FPGA XG image and initiated a 2-channel >> receive at 50MS/s (using my C++ app & UHD). To my surprise, I am getting >> frequent "timeouts" on receive, but not always at the same time. In one >> case, the receive worked successfully for 28 secs (2 ch, 50 MS/s). In >> other cases, it timed out immediately or after several seconds. Note that >> I can reliably run this same test without error if I remove the DmaFIFO. >> >> The following works fine: >> RxRadio -> DDC -> host file (in RAM file system) >> >> The following times-out at random times: >> RxRadio -> DDC -> DmaFIFO -> host file (in RAM file system) >> >> What could be the cause? Is there any reason the DmaFIFO shouldn't work >> in the receive chain? >> >> Rob >> _______________________________________________ >> USRP-users mailing list >> [email protected] >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >
_______________________________________________ USRP-users mailing list [email protected] http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
