Hello together, I have some questions concerning clock speeds and the corresponding data rates on a USRP x310 (FPGA). As far as I know, there are two different clock speeds on the FPGA, the ce_clk=200MHz, and the bus_clk - I did not find clock speed for this one.
Is it true, that the ce_clk drives my rfnoc blocks and thus my in- and outgoing data rate of each single block (using sc16 samples) is 200MHz*32 Bit/10^9 = 6,4 GBit/s? I read, that all the RFNoC Blocks are connected to the crossbar which is driven by the bus_clk. First of all: Is this the case? If so, how is the crossbar able to handle the in and output data of each RFNoC Block at once? How many Bytes can it process with each clock? Take for example the flowgraph SignalGenerator ->RFNoC-Gain -> RFNoC-DMAFIFO-> RFNoC-DUC-> RFNoC-Radio which has already four RFNoC Blocks connected to the crossbar, which in my head are 25,6 GBit/s data on the crossbar at once which seems way to much to handle. I think I really miss a point here and would be grateful for some explanation. Thanks, Felix _______________________________________________ USRP-users mailing list [email protected] http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
