Fabian, I had a hunch it was just the 3.3V part--thanks for clarifying! Cherif, the DAC interface timing (and for that matter, the ADC timing) should be fairly tight. What you're seeing is expected and matches the numbers we designed it to. The FPGA constraints are intentionally tight to provide some extra margin at the DAC. Since this is all in the same X310, you could start by isolating the various components of the design using the front-panel GPIO connector. Run a trigger from each of your custom blocks to the GPIO and see if they line up on a scope. If they don't, then you might have a baseband timing issue (with how timed commands are interacting with your blocks). If they line up, then it points to a timing failure in the DAC.
-Daniel On Fri, Sep 27, 2019 at 12:33 PM Cherif Diouf via USRP-users < usrp-users@lists.ettus.com> wrote: > fabian, > > > I have tested your solution, but the get_time_last_pps always gives me > the expect value. > > > > Daniel, On a different point, the issue might be related to timing, here > are some examples of timing related to the DACs. The compilation is > successful but the margin is very low, in the 10 ps order. > > > > > Startpoint Endpoint Slack(ns) > > > ---------------------------------------------------------------------------- > gen_db1/gen_pins[2].oddr/C DB1_DAC_D2_N 0.016 > > gen_db1/gen_pins[2].oddr/C DB1_DAC_D2_P 0.016 > > gen_db1/gen_pins[7].oddr/C DB1_DAC_D7_N 0.021 > > gen_db1/gen_pins[7].oddr/C DB1_DAC_D7_P 0.021 > > gen_db1/gen_pins[3].oddr/C DB1_DAC_D3_N 0.024 > > gen_db1/gen_pins[3].oddr/C DB1_DAC_D3_P 0.024 > > > > gen_db0/gen_pins[2].oddr/C DB0_DAC_D2_N 0.066 > > gen_db0/gen_pins[2].oddr/C DB0_DAC_D2_P 0.066 > > gen_db0/gen_pins[0].oddr/C DB0_DAC_D0_N 0.071 > > gen_db0/gen_pins[0].oddr/C DB0_DAC_D0_P 0.071 > > gen_db0/oddr_frame/C DB0_DAC_FRAME_N 0.075 > > gen_db0/oddr_frame/C DB0_DAC_FRAME_P 0.075 > > gen_db0/gen_pins[3].oddr/C DB0_DAC_D3_N 0.080 > > gen_db0/gen_pins[3].oddr/C DB0_DAC_D3_P 0.080 > > gen_db0/gen_pins[1].oddr/C DB0_DAC_D1_N 0.085 > > gen_db0/gen_pins[1].oddr/C DB0_DAC_D1_P 0.085 > > > > Best Regards > > Cherif > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > -- Daniel Jepson Digital Hardware Engineer National Instruments O: +1.512.683.6163 daniel.jep...@ni.com
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