Hi,
I am running a testbench on my architecture, and all default tests pass as
expected. This includes TEST 4 which tests writing and reading back from
registers. The problem is - the following tests prove the registers hold
their initial (default) value and not the value I tried writing to them in
TEST 4.
Did I miss something in the process?
what possible reasons may cause this problem?
Scripts of both Testbench code and NoC_block code given below.
Thanks in advance,
Ishai
*Testbench Code:*
* /******************************
**************************** ** Test 4 -- Write / readback user
registers *******************************
***************************/ `TEST_CASE_START("Write user registers");
random_word = 0; tb_streamer.write_user_reg(**sid_noc_block_TxChannelSrc,
noc_block_TxChannelSrc.SR_MIN_*
*BW, random_word[21:0]); random_word = 5;
tb_streamer.write_user_reg(**sid_noc_block_TxChannelSrc,
noc_block_TxChannelSrc.SR_MAX_*
*BW, random_word[21:0]); random_word = 10;
tb_streamer.write_user_reg(**sid_noc_block_TxChannelSrc,
noc_block_TxChannelSrc.SR_BW_*
*CHANGE_RATE, random_word[21:0]); random_word = 256;
tb_streamer.write_user_reg(**sid_noc_block_TxChannelSrc,
noc_block_TxChannelSrc.SR_PKT_*
*SIZE, random_word[15:0]); `TEST_CASE_DONE(1);*
*noc_block verilog code:*
*localparam SR_USER_REG_BASE = 129; localparam [7:0] SR_MIN_BW = 129;
//SR_USER_REG_BASE; localparam [7:0] SR_MAX_BW = 130;//TeSR_USER_REG_BASE
+ 8'd1; localparam [7:0] SR_BW_CHANGE_RATE = 131;//SR_USER_REG_BASE +
8'd2; localparam [7:0] SR_PKT_SIZE = 132; //SR_USER_REG_BASE +
8'd3; wire [15:0] payload_length; wire [21:0] min_BW; wire [21:0]
max_BW; wire [21:0] BW_change_rate; cvita_hdr_encoder
cvita_hdr_encoder ( .pkt_type(2'd0), .eob(1'b0), .has_time(1'b0),
.seqnum(12'd0), .payload_length(payload_*
*length), .dst_sid(next_dst_sid), .src_sid(src_sid), .vita_time(64'd0),
.header(s_axis_data_tuser)); // Set packet size setting_reg #(
.my_addr(SR_PKT_SIZE), .awidth(8), .width(16), .at_reset(4)) // Set a
safe default packet size in case packet size is never set
set_payload_length ( .clk(ce_clk), .rst(ce_rst), .strobe(set_stb),
.addr(set_addr), .in(set_data), .out(payload_length), .changed());
setting_reg #( .my_addr(SR_MIN_BW), .awidth(8), .width(22))
sr_min_bw ( .clk(ce_clk), .rst(ce_rst), .strobe(set_stb),
.addr(set_addr), .in(set_data), .out(min_BW), .changed()); setting_reg
#( .my_addr(SR_MAX_BW), .awidth(8), .width(22)) sr_max_bw (
.clk(ce_clk), .rst(ce_rst), .strobe(set_stb), .addr(set_addr),
.in(set_data), .out(max_BW), .changed()); setting_reg #(
.my_addr(SR_BW_CHANGE_RATE), .awidth(8), .width(22)) sr_bw_change_rate (
.clk(ce_clk), .rst(ce_rst), .strobe(set_stb), .addr(set_addr),
.in(set_data), .out(BW_change_rate), .changed()); *
--
ישי אלוש
054-5823400
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