Greetings Brian, I was having some issues with the build process, as the build script couldn't find the gain.v block file even though I was pointing the script to it. I saw that ejk github has some .inc files, so I added those and it seemed to clear up the issue. *crosses fingers* The bit file was building when I left for word this morning.
Regards, Jon On Wed, Nov 13, 2019 at 12:32 PM Jonathan Lockhart <[email protected]> wrote: > Greetings Brian, > > Thanks for the link. Yeah my Vivado always complains about the tcl cache > being unavailable unless I run as sudo. I think its b/c I installed it with > sudo, as otherwise it wouldn't make the /opt/Xilinx directory. It seems to > work either way regardless if it uses the official tcl cache or a local one. > > Anyways, that example worked out great. Now the sim could find the FPGA > repo and it tested on the 7020. I making a note of that so I can be sure to > incorporate those changes in the future for other blocks will build. > > Regards, > Jon > > On Wed, Nov 13, 2019 at 11:21 AM Brian Padalino <[email protected]> > wrote: > >> Hey Jon, >> >> On Wed, Nov 13, 2019 at 11:17 AM Jonathan Lockhart <[email protected]> >> wrote: >> >>> Greetings Brian, >>> >>> I had noticed that the script was set to use the X300 after I sent the >>> email. I switched in the CMakeList.txt file to use the e300 repo, which is >>> using the Zynq-7020, which is included in the webpack version of Vivado. I >>> unfortunately got the same error prior to the change, included below. >>> >>> ettus_sdr@ettus-VirtualBox:~/rfnoc/src/rfnoc-tutorial/build$ make >>> noc_block_gain_tb >>> Setting up a 64-bit FPGA build environment for the USRP-E3x0... >>> - Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin) >>> >>> Environment successfully initialized. >>> BUILDER: Checking tools... >>> * GNU bash, version 4.4.20(1)-release (x86_64-pc-linux-gnu) >>> * Python 2.7.15+ >>> * Vivado v2017.4.1 (64-bit) >>> >>> ****** Vivado v2017.4.1 (64-bit) >>> **** SW Build 2117270 on Tue Jan 30 15:31:13 MST 2018 >>> **** IP Build 2095745 on Tue Jan 30 17:13:15 MST 2018 >>> ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. >>> >>> CRITICAL WARNING: [Common 17-741] No write access right to the local Tcl >>> store at '/home/ettus_sdr/.Xilinx/Vivado/2017.4/XilinxTclStore'. >>> XilinxTclStore is reverted to the installation area. If you want to use >>> local Tcl Store, please change the access right and relaunch Vivado. >>> source >>> /home/ettus_sdr/rfnoc/src/uhd/fpga-src/usrp3/tools/scripts/viv_sim_project.tcl >>> >> >> This seems bad in general. Maybe because you ran it as sudo before and >> now non-sudo? >> >> >>> # set simulator $::env(VIV_SIMULATOR) >>> # set design_srcs $::env(VIV_DESIGN_SRCS) >>> # set sim_srcs $::env(VIV_SIM_SRCS) >>> # set inc_srcs $::env(VIV_INC_SRCS) >>> # set sim_top $::env(VIV_SIM_TOP) >>> # set part_name $::env(VIV_PART_NAME) >>> # set sim_runtime $::env(VIV_SIM_RUNTIME) >>> # set sim_fast $::env(VIV_SIM_FAST) >>> # set vivado_mode $::env(VIV_MODE) >>> # set working_dir [pwd] >>> # set sim_fileset "sim_1" >>> # set project_name "[string tolower $simulator]_proj" >>> # if [info exists ::env(VIV_SIM_COMPLIBDIR) ] { >>> # set sim_complibdir $::env(VIV_SIM_COMPLIBDIR) >>> # if [expr [file isdirectory $sim_complibdir] == 0] { >>> # set sim_complibdir "" >>> # } >>> # } else { >>> # set sim_complibdir "" >>> # } >>> # if [expr ([string equal $simulator "XSim"] == 0) && ([string length >>> $sim_complibdir] == 0)] { >>> # puts "BUILDER: \[ERROR\]: Could not resolve the location for the >>> compiled simulation libraries." >>> # puts " Please build libraries for chosen >>> simulator and set the env or" >>> # puts " makefile variable SIM_COMPLIBDIR to point >>> to the location." >>> # exit 1 >>> # } >>> # puts "BUILDER: Creating Vivado simulation project part $part_name" >>> BUILDER: Creating Vivado simulation project part xc7k410tffg900-2 >>> # create_project -part $part_name -force $project_name/$project_name >>> WARNING: [Device 21-436] No parts matched 'xc7k410tffg900-2' >>> ERROR: [Coretcl 2-106] Specified part could not be found. >>> INFO: [Common 17-206] Exiting Vivado at Wed Nov 13 11:07:09 2019... >>> /home/ettus_sdr/rfnoc/src/uhd/fpga-src/usrp3/top/../tools/make/viv_simulator.mak:51: >>> recipe for target 'xsim' failed >>> make[4]: *** [xsim] Error 1 >>> CMakeFiles/noc_block_gain_tb.dir/build.make:57: recipe for target >>> 'CMakeFiles/noc_block_gain_tb' failed >>> make[3]: *** [CMakeFiles/noc_block_gain_tb] Error 2 >>> CMakeFiles/Makefile2:131: recipe for target >>> 'CMakeFiles/noc_block_gain_tb.dir/all' failed >>> make[2]: *** [CMakeFiles/noc_block_gain_tb.dir/all] Error 2 >>> CMakeFiles/Makefile2:138: recipe for target >>> 'CMakeFiles/noc_block_gain_tb.dir/rule' failed >>> make[1]: *** [CMakeFiles/noc_block_gain_tb.dir/rule] Error 2 >>> Makefile:201: recipe for target 'noc_block_gain_tb' failed >>> make: *** [noc_block_gain_tb] Error 2 >>> >>> I am assuming this is the part that needs to be changed: >>> xc7k410tffg900-2. I am not seeing where this is declared in the >>> CMakeList.txt file. Do you know where I would go about changing it in the >>> build scripts? >>> >> >> Yeah, change it over. I use EJ's repository as a good example for lots >> of stuff. Particularly this: >> >> >> https://github.com/ejk43/rfnoc-ootexample/blob/master/rfnoc/testbenches/noc_block_complextomagphase_tb/Makefile#L14 >> >> Just override it in the Makefile like EJ does there. >> >> Let us know how that works out? >> >> Brian >> >>>
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