Wheberth, The source code for any of the NI-USRP side of things is locked down. Even if I thought is was something that would be useful in this case (I'm still not convinced it would be), it's not something I'm at liberty to release. However, from your email, it sounds like the main hesitation here is the level of effort associated with duplication of your IP. It may be useful for you to know that as of LabVIEW 2018, you can export your LabVIEW FPGA IP for use in Vivado:
Exporting FPGA VIs as Vivado Design Suite Projects (FPGA Module) https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpgahelp/export_fpga_vis_howto/ As I said before, this kind of thing isn't something I'm familiar with, so follow up questions on that Export Tool should be directed to NI Support. If you'd like to have a deeper discussion on why I don't think that the HG.lvbitx source code will be particularly helpful to you, send me a direct email and we can chat about it off of the mailing list -- it's not exactly relevant to the open source side of things. Sam On Thu, Dec 5, 2019 at 11:23 AM Wheberth Damascena Dias <whebe...@gmail.com> wrote: > HI Sam, > > Thank you for your answer. > Let me explain our situation a little bit better. Here at Inatel we have > been developing for the USRPs using the LabVIEW FPGA (USRP-RIO) flow for a > while. So we have many blocks already implemented in this paradigm. We are > now switching for the software flow using GNU Radio, due to the development > agility it provides compared to any FPGA flow. Although, for some blocks, > is very difficult to achieve the required processing throughput in a > software implementation. The Digital pre-distorter is one of those. The > bandwidth required at the output of this block must be many times (3x to > 5x) the bandwidth of the desired signal. Then an hybrid approach with FPGA > and as software development is needed. > As pointed out in the previous message, it turns out that the stock USRP > images were generated using the same tool we have been using by tha last 4 > years, This way, if we could modify the stock image, using the LabVIEW flow > and could insert the DPD block just before the DAC output (running at the > master_clock_rate 200MHz or 184.32MHz) it would be a perfect fit for our > need. So if that code were available it would be straightforward to us to > do this modification (Depending on the LabVIEW version). > I know that is not the intended flow, but that source code would be really > helpful, if available. > > Best Regards, > > > > Em qui., 5 de dez. de 2019 às 13:30, Sam Reiter <sam.rei...@ettus.com> > escreveu: > >> Wheberth, >> >> What you're trying to do sounds possible, but I think you're approaching >> it the wrong way. When you use the USRP with a default FPGA image >> (usrp_x310_fpga_HG.lvbitx), you just get the HG image that you can >> interface with using the NI-USRP driver in LabVIEW. In that case, >> everything you program is on the host side. With this HG image, you're >> pretty much just getting default RFNoC under the hood with a few changes >> including header modifications. The project isn't available and wouldn't be >> useful to you for integrating your code, even if you had it. >> >> You'll want to use your X310 as a USRP RIO and interact with it via the >> LabVIEW FPGA module (or something along those lines, I'm not particularly >> familiar with this paradigm myself). This will give you a blank block >> diagram to implement your IP and pass data over DMA to the host while >> preserving the static logic necessary to allow the radio to work as you'd >> expect. This is all LabVIEW and no UHD/GR. You might poke around some of >> the USRP RIO examples [1] to see how similar functionality has been >> implemented before you drop yours in. Beyond that, reaching out to NI >> Support might be a good call for follow up questions. >> >> Sam Reiter >> Ettus Research >> >> [1] >> https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019TmVSAU&l=en-US >> >> On Thu, Dec 5, 2019 at 7:13 AM Wheberth Damascena Dias via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >>> >>> Hi All, >>> >>> Looking at the bitfile "usrp_x310_fpga_HG.lvbitx", as the name suggests, >>> it looks like it came from LabVIEW/LabVIEW Comms. It is possible even to >>> see the top ..vi filename which is "USRP_X3x0_Top.vi". >>> Although I wasn't able to find the LabVIEW source project for this >>> bitfile. Is this source available anywhere? >>> I am asking, because we have to include some custom code (a digital >>> baseband pre-distorter) to run on the USRP FPGA. As we already have this >>> implemented in LabVIEW it would save us a lot of time comparing to going >>> through the RFNoC route. >>> >>> Thank you in advance, >>> Best Regards >>> -- >>> *Wheberth Damascena Dias* >>> _______________ _____ _____ __ ___ __ _ _ _ _ >>> http://www.linkedin.com/in/wheberth >>> e-mail:whebe...@gmail.com >>> >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >> > > -- > *Wheberth Damascena Dias* > _______________ _____ _____ __ ___ __ _ _ _ _ > http://www.linkedin.com/in/wheberth > e-mail:whebe...@gmail.com > >
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