Hi Varban, not quite sure I understand what you want: The B2xx series only has the streamers it has, so you can either get the DDC output, or the output of your module, not both (unless you somehow interleave them, and then on the host deinterleave them).
Also, unless latency is an important constraint: since the B205mini can basically output samples at ADC speed, what's the specific motivation to do things on the FPGA? Best regards, Marcus On Tue, 2019-12-31 at 18:11 +0200, Varban Metodiev via USRP-users wrote: > Dear all, > > I have written a simple RX logic in Verilog and now I want to > integrate it inside the FPGA. I have the following questions: > > 1) What is the correct way to connect it after the DDC (so that I > will get 1:1 samples with those from GNURadio)? > 2) How should I expose it to the UHD driver? I read the > radio_legacy.v example about the custom UHD registers but I couldn't > get how to specify the register address mapping. > > Thank you in advance, > Varban > _______________________________________________ > USRP-users mailing list > [email protected] > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com _______________________________________________ USRP-users mailing list [email protected] http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
