On 01/21/2020 05:06 AM, Arash Jafari via USRP-users wrote:
Hello Everybody,
according to FPGA implementation of my board which a USRP-b200, the
Least significant 4bits of I or Q samples are always 0 (0x???0), which
in turn means the recorded sample as short complex 16 bits (sc16) cpu
format should have four zero at LSB.
But almost 10% of recorded samples do not obey this rule!!!!
Any comment is highly appreciated!
Kind regards,
This is because the FPGA implementation always scales the ADC values to
whatever is appropriate for the wire format, which by default
is 16-bits.
The idea is to make the sample formats somewhat independent from the ADC
of whatever hardware you happen to be using. This happens
both implicitly, by virtue of the way a fixed-point DDC operates, and
explicitly by scaling code in the FPGA.
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