Hi Jonathon,
After separating the I and Q channels, I think that the values with
detached RX input look reasonable (please see *I_Q_data_custom_build.txt*).
What do you think?
I am reading my custom register with a modified version of
*rx_samples_to_file* (attached as well, line 92 - 100).
Now, when I try to send some reference sine waves via the *tx_waveforms*
example running on another PC attached to another USRP B205mini, I get
unexplainable data.
The default data type in the *tx_waveforms* is fc32, do I need to recompile
it with sc16 for this case?
Kind regards,
V.
On Wed, Feb 26, 2020 at 1:36 AM Varban Metodiev <[email protected]>
wrote:
> Hi Jonathon,
>
> Thank you very much for your reply.
>
> What do you want to accomplish?
> --> Right now, I just want to monitor the 'sample_rx' values. Eventually,
> I will use this to calibrate the reference input of my custom Verilog
> decoder (attached) that aims to detect spikes and measure their length
> (like those from the attachment).
>
> It is a short complex int where the upper 16-bits are I and the lower
> 16-bits are Q.
> --> Well... that could be the explanation. I will try to monitor them
> separately and get back to you.
>
> Kind regards,
> Varban
>
> On Tue, Feb 25, 2020 at 8:50 PM Jonathon Pendlum <
> [email protected]> wrote:
>
>> Hi Varban,
>>
>> I am now getting random 32-bit values when polling it from the UHD
>>> (instead of a constant that indicates a "zero" reception)
>>
>>
>> Even with the antenna disconnected you can expect some LSBs to toggle due
>> to inherent receiver noise.
>>
>> 1) How should I interpret the 32-variable?
>>>
>>
>> It is a short complex int where the upper 16-bits are I and the lower
>> 16-bits are Q.
>>
>>
>>> 2) Is the strobe_rx the correct signal that indicates new sample arrival?
>>>
>>
>> Yes
>>
>>
>>> 2) Do I need new_rx_control?
>>
>>
>> No
>>
>> Have I done this correctly in general, or there is something completely
>>> wrong in my approach?
>>
>>
>> What do you want to accomplish?
>>
>> Jonathon
>>
>> On Mon, Feb 17, 2020 at 5:03 AM Varban Metodiev via USRP-users <
>> [email protected]> wrote:
>>
>>> Dear all,
>>>
>>> After exposing the *sample_rx* from radio_legacy.v
>>> <https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/lib/radio_200/radio_legacy.v>
>>> to
>>> a user defined register and sampling it at rising edge of the
>>> *strobe_rx*, I am now getting random 32-bit values when polling it from
>>> the UHD (instead of a constant that indicates a "zero" reception). I am
>>> doing this with disconnected antenna using a modified rx_samples C++
>>> example application.
>>>
>>> I have the following questions:
>>> 1) How should I interpret the 32-variable?
>>> 2) Is the strobe_rx the correct signal that indicates new sample arrival?
>>> 2) Do I need new_rx_control?
>>>
>>> Have I done this correctly in general, or there is something completely
>>> wrong in my approach?
>>>
>>> Thanks,
>>> Varban
>>> _______________________________________________
>>> USRP-users mailing list
>>> [email protected]
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>
vmetodiev@ubuntu:~/Development/SDR/uhd/host/build/examples$ sudo
./rx_samples_to_file --freq 2e9 --rate 1e6 --bw 1e6 --gain 60
Creating the usrp device with: ...
[INFO] [UHD] linux; GNU C++ version 9.2.1 20191008; Boost_106700;
UHD_4.0.0.0-436-g45719260
[INFO] [B200] Detected Device: B205mini
[INFO] [B200] Operating over USB 3.
[INFO] [B200] Initialize CODEC control...
[INFO] [B200] Initialize Radio control...
[INFO] [B200] Performing register loopback test...
[INFO] [B200] Register loopback test passed
[INFO] [B200] Setting master clock rate selection to 'automatic'.
[INFO] [B200] Asking for clock rate 16.000000 MHz...
[INFO] [B200] Actually got clock rate 16.000000 MHz.
Using Device: Single USRP:
Device: B-Series Device
Mboard 0: B205mini
RX Channel: 0
RX DSP: 0
RX Dboard: A
RX Subdev: FE-RX1
TX Channel: 0
TX DSP: 0
TX Dboard: A
TX Subdev: FE-TX1
Setting RX Rate: 1.000000 Msps...
[INFO] [B200] Asking for clock rate 32.000000 MHz...
[INFO] [B200] Actually got clock rate 32.000000 MHz.
Actual RX Rate: 1.000000 Msps...
Setting RX Freq: 2000.000000 MHz...
Setting RX LO Offset: 0.000000 MHz...
Actual RX Freq: 2000.000000 MHz...
Setting RX Gain: 60.000000 dB...
Actual RX Gain: 60.000000 dB...
Setting RX Bandwidth: 1.000000 MHz...
Actual RX Bandwidth: 1.000000 MHz...
Waiting for "lo_locked": ++++++++++ locked.
Press Ctrl + C to stop streaming...
I: 26
Q: 6
-------------
I: -46
Q: -30
-------------
I: -43
Q: -3
-------------
I: -39
Q: -24
-------------
I: 21
Q: -15
-------------
I: -22
Q: 70
-------------
I: -13
Q: 29
-------------
I: -4
Q: 0
-------------
I: 14
Q: 13
-------------
I: -51
Q: -36
-------------
I: -16
Q: 37
-------------
I: -10
Q: -25
-------------
I: 20
Q: 23
-------------
I: -66
Q: -49
-------------
I: -3
Q: -18
-------------
I: 14
Q: 4
-------------
I: -7
Q: 22
-------------
I: -31
Q: 32
-------------
I: 21
Q: 28
-------------
I: -26
Q: 1
-------------
I: -23
Q: 37
-------------
I: 8
Q: 12
-------------
I: -14
Q: 13
-------------
I: -1
Q: -25
-------------
I: -76
Q: 50
-------------
I: 50
Q: -39
-------------
I: -22
Q: 5
-------------
I: 7
Q: -46
-------------
I: -51
Q: -3
-------------
I: 3
Q: -35
-------------
I: 10
Q: -63
-------------
I: -8
Q: -51
-------------
I: -36
Q: -43
-------------
I: 26
Q: 54
-------------
I: -19
Q: -36
-------------
I: 38
Q: 24
-------------
I: -28
Q: 22
-------------
I: -23
Q: -7
-------------
I: 16
Q: 17
-------------
I: 21
Q: 2
-------------
I: -13
Q: -30
-------------
I: 49
Q: -14
-------------
I: -55
Q: -21
-------------
I: -22
Q: 62
-------------
I: 24
Q: -37
-------------
I: 12
Q: 12
-------------
I: 1
Q: 19
-------------
I: -46
Q: 43
-------------
I: 48
Q: -68
-------------
I: 16
Q: -20
-------------
I: -35
Q: -34
-------------
I: -30
Q: -25
-------------
I: -45
Q: 0
-------------
I: 17
Q: 6
-------------
I: -68
Q: -40
-------------
I: -28
Q: -29
-------------
I: 41
Q: 32
-------------
I: -4
Q: 16
-------------
I: 3
Q: 1
-------------
I: 18
Q: -33
-------------
I: 39
Q: 38
-------------
I: -19
Q: -11
-------------
I: 19
Q: -22
-------------
I: -22
Q: 38
-------------
I: -27
Q: 24
-------------
I: 27
Q: -2
-------------
I: -23
Q: -42
-------------
I: 8
Q: -56
-------------
I: -6
Q: -21
-------------
I: -8
Q: 13
-------------
I: 9
Q: 34
-------------
I: 29
Q: 37
-------------
I: -37
Q: -30
-------------
I: -45
Q: -21
-------------
I: 6
Q: -39
-------------
I: 33
Q: -40
-------------
I: -47
Q: 35
-------------
I: 45
Q: -14
-------------
I: 3
Q: 32
-------------
I: 19
Q: -13
-------------
I: -2
Q: 22
-------------
I: 4
Q: 70
-------------
I: -35
Q: -44
-------------
I: -10
Q: -44
-------------
I: 13
Q: -41
-------------
I: 28
Q: 17
-------------
I: -26
Q: -3
-------------
I: 32
Q: 22
-------------
I: -24
Q: -36
-------------
I: -12
Q: 20
-------------
I: 4
Q: 21
-------------
I: -24
Q: 5
-------------
I: -18
Q: -48
-------------
I: -31
Q: 51
-------------
I: -11
Q: 31
-------------
I: 26
Q: 0
-------------
I: 23
Q: 8
-------------
I: -28
Q: -10
-------------
I: 41
Q: -6
-------------
I: -26
Q: 1
-------------
I: 25
Q: -42
-------------
I: -8
Q: -8
-------------
I: 56
Q: 7
-------------
I: -67
Q: 32
-------------
I: -10
Q: -46
-------------
I: 31
Q: -60
-------------
I: -29
Q: -82
-------------
I: -74
Q: -17
-------------
I: 24
Q: 42
-------------
I: -16
Q: -44
-------------
I: 62
Q: 34
-------------
I: -11
Q: -17
-------------
I: -46
Q: -11
-------------
I: 23
Q: -5
-------------
I: 67
Q: 73
-------------
I: 31
Q: 26
-------------
I: -17
Q: 56
-------------
I: -35
Q: -53
-------------
I: 36
Q: 6
-------------
I: -84
Q: -53
-------------
I: 32
Q: -56
-------------
I: 34
Q: -14
-------------
I: -79
Q: 6
-------------
I: -76
Q: 2
-------------
I: -30
Q: 9
-------------
I: -5
Q: -17
-------------
I: -8
Q: 65
-------------
I: -21
Q: -25
-------------
I: 23
Q: 36
-------------
I: -24
Q: 9
-------------
I: -22
Q: 41
-------------
I: -62
Q: 60
-------------
I: 49
Q: -6
-------------
I: -11
Q: -38
-------------
I: 70
Q: 15
-------------
I: 27
Q: -9
-------------
I: -52
Q: 11
-------------
I: 53
Q: -20
-------------
I: 67
Q: -35
-------------
I: -18
Q: 36
-------------
I: 49
Q: 5
-------------
I: -21
Q: 48
-------------
I: 42
Q: 9
-------------
I: -47
Q: 8
-------------
I: 3
Q: -52
-------------
I: 42
Q: 9
-------------
I: -21
Q: -28
-------------
I: -52
Q: -81
-------------
I: -57
Q: -50
-------------
I: 59
Q: -14
-------------
I: 20
Q: 14
-------------
I: -66
Q: -1
-------------
I: -69
Q: 4
-------------
I: 21
Q: -51
-------------
I: 16
Q: -31
-------------
I: -66
Q: 23
-------------
I: -5
Q: -75
-------------
I: 67
Q: 2
-------------
I: 28
Q: -14
-------------
I: 51
Q: 38
-------------
I: 47
Q: -89
-------------
I: 49
Q: -52
-------------
I: 55
Q: -48
-------------
I: 66
Q: -9
-------------
I: -44
Q: -39
-------------
I: -55
Q: -5
-------------
I: 75
Q: -12
-------------
I: 43
Q: 68
-------------
I: -35
Q: -36
-------------
I: 114
Q: -33
-------------
I: -15
Q: -24
-------------
I: 29
Q: -25
-------------
I: 8
Q: -22
-------------
I: 28
Q: 2
-------------
I: 0
Q: 13
-------------
I: 18
Q: -24
-------------
I: 28
Q: -2
-------------
I: -83
Q: 14
-------------
I: -29
Q: -6
-------------
I: -24
Q: -51
-------------
I: -20
Q: -26
-------------
I: 32
Q: -42
-------------
I: 20
Q: -52
-------------
I: -44
Q: -39
-------------
I: -43
Q: -52
-------------
I: 10
Q: 31
-------------
I: 19
Q: 16
-------------
I: -32
Q: -43
-------------
I: 15
Q: 11
-------------
I: 58
Q: -35
-------------
I: 0
Q: 58
-------------
I: -6
Q: 39
-------------
I: 2
Q: 32
-------------
I: 1
Q: 11
-------------
I: 45
Q: -11
-------------
I: -35
Q: -44
-------------
I: -3
Q: 39
-------------
I: 24
Q: 44
-------------
I: 3
Q: 43
-------------
I: -27
Q: -45
-------------
I: 6
Q: 37
-------------
I: 14
Q: -1
-------------
I: 32
Q: -22
-------------
//
// Copyright 2010-2011,2014 Ettus Research LLC
// Copyright 2018 Ettus Research, a National Instruments Company
//
// SPDX-License-Identifier: GPL-3.0-or-later
//
#include <uhd/exception.hpp>
#include <uhd/types/tune_request.hpp>
#include <uhd/usrp/multi_usrp.hpp>
#include <uhd/utils/safe_main.hpp>
#include <uhd/utils/thread.hpp>
#include <boost/format.hpp>
#include <boost/lexical_cast.hpp>
#include <boost/program_options.hpp>
#include <chrono>
#include <complex>
#include <csignal>
#include <fstream>
#include <iostream>
#include <thread>
namespace po = boost::program_options;
static bool stop_signal_called = false;
void sig_int_handler(int)
{
stop_signal_called = true;
}
template <typename samp_type>
void recv_to_file(uhd::usrp::multi_usrp::sptr usrp,
const std::string& cpu_format,
const std::string& wire_format,
const size_t& channel,
const std::string& file,
size_t samps_per_buff,
unsigned long long num_requested_samples,
double time_requested = 0.0,
bool bw_summary = false,
bool stats = false,
bool null = false,
bool enable_size_map = false,
bool continue_on_bad_packet = false)
{
unsigned long long num_total_samps = 0;
// create a receive streamer
uhd::stream_args_t stream_args(cpu_format, wire_format);
std::vector<size_t> channel_nums;
channel_nums.push_back(channel);
stream_args.channels = channel_nums;
uhd::rx_streamer::sptr rx_stream = usrp->get_rx_stream(stream_args);
uhd::rx_metadata_t md;
std::vector<samp_type> buff(samps_per_buff);
std::ofstream outfile;
if (not null)
outfile.open(file.c_str(), std::ofstream::binary);
bool overflow_message = true;
// setup streaming
uhd::stream_cmd_t stream_cmd((num_requested_samples == 0)
? uhd::stream_cmd_t::STREAM_MODE_START_CONTINUOUS
: uhd::stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE);
stream_cmd.num_samps = size_t(num_requested_samples);
stream_cmd.stream_now = true;
stream_cmd.time_spec = uhd::time_spec_t();
rx_stream->issue_stream_cmd(stream_cmd);
typedef std::map<size_t, size_t> SizeMap;
SizeMap mapSizes;
const auto start_time = std::chrono::steady_clock::now();
const auto stop_time =
start_time + std::chrono::milliseconds(int64_t(1000 * time_requested));
// Track time and samps between updating the BW summary
auto last_update = start_time;
unsigned long long last_update_samps = 0;
// Run this loop until either time expired (if a duration was given), until
// the requested number of samples were collected (if such a number was
// given), or until Ctrl-C was pressed.
while (not stop_signal_called
and (num_requested_samples != num_total_samps or num_requested_samples == 0)
and (time_requested == 0.0 or std::chrono::steady_clock::now() <= stop_time)) {
const auto now = std::chrono::steady_clock::now();
// Read USER REGISTERS here
auto regs = usrp->get_user_settings_iface();
//regs->poke32(0, 0xCAFE);
//regs->poke32(4, 0xBEEF);
short i_chan = 0;
short q_chan = 0;
auto iq_chans = (regs->peek64(0)) & 0x00000000FFFFFFFF; // Because we use the lower 32 bits in the custom FPGA build for storing the current sample_rx
i_chan = (iq_chans >> 16) & 0x0000FFFF;
q_chan = 0x0000FFFF & iq_chans;
std::cout << boost::format("I: %hi\n") % i_chan;
std::cout << boost::format("Q: %hi\n") % q_chan;
std::cout << boost::format("-------------\n");
size_t num_rx_samps =
rx_stream->recv(&buff.front(), buff.size(), md, 3.0, enable_size_map);
if (md.error_code == uhd::rx_metadata_t::ERROR_CODE_TIMEOUT) {
std::cout << boost::format("Timeout while streaming") << std::endl;
break;
}
if (md.error_code == uhd::rx_metadata_t::ERROR_CODE_OVERFLOW) {
if (overflow_message) {
overflow_message = false;
std::cerr
<< boost::format(
"Got an overflow indication. Please consider the following:\n"
" Your write medium must sustain a rate of %fMB/s.\n"
" Dropped samples will not be written to the file.\n"
" Please modify this example for your purposes.\n"
" This message will not appear again.\n")
% (usrp->get_rx_rate(channel) * sizeof(samp_type) / 1e6);
}
continue;
}
if (md.error_code != uhd::rx_metadata_t::ERROR_CODE_NONE) {
std::string error = str(boost::format("Receiver error: %s") % md.strerror());
if (continue_on_bad_packet) {
std::cerr << error << std::endl;
continue;
} else
throw std::runtime_error(error);
}
if (enable_size_map) {
SizeMap::iterator it = mapSizes.find(num_rx_samps);
if (it == mapSizes.end())
mapSizes[num_rx_samps] = 0;
mapSizes[num_rx_samps] += 1;
}
num_total_samps += num_rx_samps;
if (outfile.is_open()) {
outfile.write((const char*)&buff.front(), num_rx_samps * sizeof(samp_type));
}
if (bw_summary) {
last_update_samps += num_rx_samps;
const auto time_since_last_update = now - last_update;
if (time_since_last_update > std::chrono::seconds(1)) {
const double time_since_last_update_s =
std::chrono::duration<double>(time_since_last_update).count();
const double rate = double(last_update_samps) / time_since_last_update_s;
std::cout << "\t" << (rate / 1e6) << " Msps" << std::endl;
last_update_samps = 0;
last_update = now;
}
}
}
const auto actual_stop_time = std::chrono::steady_clock::now();
stream_cmd.stream_mode = uhd::stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS;
rx_stream->issue_stream_cmd(stream_cmd);
if (outfile.is_open()) {
outfile.close();
}
if (stats) {
std::cout << std::endl;
const double actual_duration_seconds =
std::chrono::duration<float>(actual_stop_time - start_time).count();
std::cout << boost::format("Received %d samples in %f seconds") % num_total_samps
% actual_duration_seconds
<< std::endl;
const double rate = (double)num_total_samps / actual_duration_seconds;
std::cout << (rate / 1e6) << " Msps" << std::endl;
if (enable_size_map) {
std::cout << std::endl;
std::cout << "Packet size map (bytes: count)" << std::endl;
for (SizeMap::iterator it = mapSizes.begin(); it != mapSizes.end(); it++)
std::cout << it->first << ":\t" << it->second << std::endl;
}
}
}
typedef std::function<uhd::sensor_value_t(const std::string&)> get_sensor_fn_t;
bool check_locked_sensor(std::vector<std::string> sensor_names,
const char* sensor_name,
get_sensor_fn_t get_sensor_fn,
double setup_time)
{
if (std::find(sensor_names.begin(), sensor_names.end(), sensor_name)
== sensor_names.end())
return false;
auto setup_timeout = std::chrono::steady_clock::now()
+ std::chrono::milliseconds(int64_t(setup_time * 1000));
bool lock_detected = false;
std::cout << boost::format("Waiting for \"%s\": ") % sensor_name;
std::cout.flush();
while (true) {
if (lock_detected and (std::chrono::steady_clock::now() > setup_timeout)) {
std::cout << " locked." << std::endl;
break;
}
if (get_sensor_fn(sensor_name).to_bool()) {
std::cout << "+";
std::cout.flush();
lock_detected = true;
} else {
if (std::chrono::steady_clock::now() > setup_timeout) {
std::cout << std::endl;
throw std::runtime_error(
str(boost::format(
"timed out waiting for consecutive locks on sensor \"%s\"")
% sensor_name));
}
std::cout << "_";
std::cout.flush();
}
std::this_thread::sleep_for(std::chrono::milliseconds(100));
}
std::cout << std::endl;
return true;
}
int UHD_SAFE_MAIN(int argc, char* argv[])
{
// variables to be set by po
std::string args, file, type, ant, subdev, ref, wirefmt;
size_t channel, total_num_samps, spb;
double rate, freq, gain, bw, total_time, setup_time, lo_offset;
// setup the program options
po::options_description desc("Allowed options");
// clang-format off
desc.add_options()
("help", "help message")
("args", po::value<std::string>(&args)->default_value(""), "multi uhd device address args")
("file", po::value<std::string>(&file)->default_value("usrp_samples.dat"), "name of the file to write binary samples to")
("type", po::value<std::string>(&type)->default_value("short"), "sample type: double, float, or short")
("nsamps", po::value<size_t>(&total_num_samps)->default_value(0), "total number of samples to receive")
("duration", po::value<double>(&total_time)->default_value(0), "total number of seconds to receive")
("spb", po::value<size_t>(&spb)->default_value(10000), "samples per buffer")
("rate", po::value<double>(&rate)->default_value(1e6), "rate of incoming samples")
("freq", po::value<double>(&freq)->default_value(0.0), "RF center frequency in Hz")
("lo-offset", po::value<double>(&lo_offset)->default_value(0.0),
"Offset for frontend LO in Hz (optional)")
("gain", po::value<double>(&gain), "gain for the RF chain")
("ant", po::value<std::string>(&ant), "antenna selection")
("subdev", po::value<std::string>(&subdev), "subdevice specification")
("channel", po::value<size_t>(&channel)->default_value(0), "which channel to use")
("bw", po::value<double>(&bw), "analog frontend filter bandwidth in Hz")
("ref", po::value<std::string>(&ref)->default_value("internal"), "reference source (internal, external, mimo)")
("wirefmt", po::value<std::string>(&wirefmt)->default_value("sc16"), "wire format (sc8, sc16 or s16)")
("setup", po::value<double>(&setup_time)->default_value(1.0), "seconds of setup time")
("progress", "periodically display short-term bandwidth")
("stats", "show average bandwidth on exit")
("sizemap", "track packet size and display breakdown on exit")
("null", "run without writing to file")
("continue", "don't abort on a bad packet")
("skip-lo", "skip checking LO lock status")
("int-n", "tune USRP with integer-N tuning")
;
// clang-format on
po::variables_map vm;
po::store(po::parse_command_line(argc, argv, desc), vm);
po::notify(vm);
// print the help message
if (vm.count("help")) {
std::cout << boost::format("UHD RX samples to file %s") % desc << std::endl;
std::cout << std::endl
<< "This application streams data from a single channel of a USRP "
"device to a file.\n"
<< std::endl;
return ~0;
}
bool bw_summary = vm.count("progress") > 0;
bool stats = vm.count("stats") > 0;
bool null = vm.count("null") > 0;
bool enable_size_map = vm.count("sizemap") > 0;
bool continue_on_bad_packet = vm.count("continue") > 0;
if (enable_size_map)
std::cout << "Packet size tracking enabled - will only recv one packet at a time!"
<< std::endl;
// create a usrp device
std::cout << std::endl;
std::cout << boost::format("Creating the usrp device with: %s...") % args
<< std::endl;
std::string myvar = "type=b200,enable_user_regs";
uhd::usrp::multi_usrp::sptr usrp = uhd::usrp::multi_usrp::make(myvar);
// Lock mboard clocks
if (vm.count("ref")) {
usrp->set_clock_source(ref);
}
// always select the subdevice first, the channel mapping affects the other settings
if (vm.count("subdev"))
usrp->set_rx_subdev_spec(subdev);
std::cout << boost::format("Using Device: %s") % usrp->get_pp_string() << std::endl;
// set the sample rate
if (rate <= 0.0) {
std::cerr << "Please specify a valid sample rate" << std::endl;
return ~0;
}
std::cout << boost::format("Setting RX Rate: %f Msps...") % (rate / 1e6) << std::endl;
usrp->set_rx_rate(rate, channel);
std::cout << boost::format("Actual RX Rate: %f Msps...")
% (usrp->get_rx_rate(channel) / 1e6)
<< std::endl
<< std::endl;
// set the center frequency
if (vm.count("freq")) { // with default of 0.0 this will always be true
std::cout << boost::format("Setting RX Freq: %f MHz...") % (freq / 1e6)
<< std::endl;
std::cout << boost::format("Setting RX LO Offset: %f MHz...") % (lo_offset / 1e6)
<< std::endl;
uhd::tune_request_t tune_request(freq, lo_offset);
if (vm.count("int-n"))
tune_request.args = uhd::device_addr_t("mode_n=integer");
usrp->set_rx_freq(tune_request, channel);
std::cout << boost::format("Actual RX Freq: %f MHz...")
% (usrp->get_rx_freq(channel) / 1e6)
<< std::endl
<< std::endl;
}
// set the rf gain
if (vm.count("gain")) {
std::cout << boost::format("Setting RX Gain: %f dB...") % gain << std::endl;
usrp->set_rx_gain(gain, channel);
std::cout << boost::format("Actual RX Gain: %f dB...")
% usrp->get_rx_gain(channel)
<< std::endl
<< std::endl;
}
// set the IF filter bandwidth
if (vm.count("bw")) {
std::cout << boost::format("Setting RX Bandwidth: %f MHz...") % (bw / 1e6)
<< std::endl;
usrp->set_rx_bandwidth(bw, channel);
std::cout << boost::format("Actual RX Bandwidth: %f MHz...")
% (usrp->get_rx_bandwidth(channel) / 1e6)
<< std::endl
<< std::endl;
}
// set the antenna
if (vm.count("ant"))
usrp->set_rx_antenna(ant, channel);
std::this_thread::sleep_for(std::chrono::milliseconds(int64_t(1000 * setup_time)));
// check Ref and LO Lock detect
if (not vm.count("skip-lo")) {
check_locked_sensor(usrp->get_rx_sensor_names(channel),
"lo_locked",
[usrp, channel](const std::string& sensor_name) {
return usrp->get_rx_sensor(sensor_name, channel);
},
setup_time);
if (ref == "mimo") {
check_locked_sensor(usrp->get_mboard_sensor_names(0),
"mimo_locked",
[usrp](const std::string& sensor_name) {
return usrp->get_mboard_sensor(sensor_name);
},
setup_time);
}
if (ref == "external") {
check_locked_sensor(usrp->get_mboard_sensor_names(0),
"ref_locked",
[usrp](const std::string& sensor_name) {
return usrp->get_mboard_sensor(sensor_name);
},
setup_time);
}
}
if (total_num_samps == 0) {
std::signal(SIGINT, &sig_int_handler);
std::cout << "Press Ctrl + C to stop streaming..." << std::endl;
}
#define recv_to_file_args(format) \
(usrp, \
format, \
wirefmt, \
channel, \
file, \
spb, \
total_num_samps, \
total_time, \
bw_summary, \
stats, \
null, \
enable_size_map, \
continue_on_bad_packet)
// recv to file
if (wirefmt == "s16") {
if (type == "double")
recv_to_file<double> recv_to_file_args("f64");
else if (type == "float")
recv_to_file<float> recv_to_file_args("f32");
else if (type == "short")
recv_to_file<short> recv_to_file_args("s16");
else
throw std::runtime_error("Unknown type " + type);
} else {
if (type == "double")
recv_to_file<std::complex<double>> recv_to_file_args("fc64");
else if (type == "float")
recv_to_file<std::complex<float>> recv_to_file_args("fc32");
else if (type == "short")
recv_to_file<std::complex<short>> recv_to_file_args("sc16");
else
throw std::runtime_error("Unknown type " + type);
}
// finished
std::cout << std::endl << "Done!" << std::endl << std::endl;
return EXIT_SUCCESS;
}
//
// Copyright 2013 Ettus Research LLC
// Copyright 2018 Ettus Research, a National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// radio top level module for b200
// Contains all clock-rate DSP components, all radio and hardware controls and settings
module radio_legacy
#(
parameter RADIO_FIFO_SIZE = 13,
parameter SAMPLE_FIFO_SIZE = 11,
parameter FP_GPIO = 0,
parameter NEW_HB_INTERP = 0,
parameter NEW_HB_DECIM = 0,
parameter SOURCE_FLOW_CONTROL = 0,
parameter USER_SETTINGS = 1,
parameter DEVICE = "SPARTAN6"
)
(input radio_clk, input radio_rst,
input [31:0] rx, output reg [31:0] tx,
input [31:0] fe_gpio_in, output [31:0] fe_gpio_out, output [31:0] fe_gpio_ddr,
input [9:0] fp_gpio_in, output [9:0] fp_gpio_out, output [9:0] fp_gpio_ddr,
input pps, input time_sync,
input bus_clk, input bus_rst,
input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready,
output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready,
input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready,
output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready,
output reg [63:0] vita_time_b,
output [63:0] debug
);
// ////////////////////////////////////////////////////////////////////////////////
// Interconnects for the user defined registers
wire [31:0] user_reg_0_value, user_reg_1_value, curr_sample_reg_value;
wire [15:0] decoded_symbol_value;
reg [31:0] curr_sample_reg;
// ///////////////////////////////////////////////////////////////////////////////
// FIFO Interfacing to the bus clk domain
// in_tdata splits to tx_tdata and ctrl_tdata
// rx_tdata and resp_tdata get muxed to out_tdata
// Everything except rx flow control must cross in to radio_clk domain before further use
// _b signifies bus_clk domain, _r signifies radio_clk domain
wire [63:0] ctrl_tdata_r;
wire ctrl_tready_r, ctrl_tvalid_r;
wire ctrl_tlast_r;
wire [63:0] resp_tdata_r;
wire resp_tready_r, resp_tvalid_r;
wire resp_tlast_r;
wire [63:0] rx_tdata_r;
wire rx_tready_r, rx_tvalid_r;
wire rx_tlast_r;
wire [63:0] rx_err_tdata_r;
wire rx_err_tready_r, rx_err_tvalid_r;
wire rx_err_tlast_r;
wire [63:0] rx_prefc_tdata_r;
wire rx_prefc_tready_r, rx_prefc_tvalid_r;
wire rx_prefc_tlast_r;
wire [63:0] rx_postfc_tdata_r;
wire rx_postfc_tready_r, rx_postfc_tvalid_r;
wire rx_postfc_tlast_r;
wire [63:0] tx_tdata_r;
wire tx_tready_r, tx_tvalid_r;
wire tx_tlast_r;
wire [63:0] txresp_tdata, txresp_tdata_r;
wire txresp_tready, txresp_tready_r, txresp_tvalid, txresp_tvalid_r;
wire txresp_tlast, txresp_tlast_r;
wire [63:0] rmux_tdata_r;
wire rmux_tlast_r, rmux_tvalid_r, rmux_tready_r;
wire [31:0] tx_idle;
wire [3:0] ibs_state;
wire [63:0] rx_tdata_int;
wire rx_tready_int, rx_tvalid_int;
wire rx_tlast_int;
axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) ctrl_fifo
(.reset(bus_rst),
.i_aclk(bus_clk), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .i_tdata({ctrl_tlast, ctrl_tdata}),
.o_aclk(radio_clk), .o_tvalid(ctrl_tvalid_r), .o_tready(ctrl_tready_r), .o_tdata({ctrl_tlast_r, ctrl_tdata_r}));
axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) tx_fifo
(.reset(bus_rst),
.i_aclk(bus_clk), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .i_tdata({tx_tlast, tx_tdata}),
.o_aclk(radio_clk), .o_tvalid(tx_tvalid_r), .o_tready(tx_tready_r), .o_tdata({tx_tlast_r, tx_tdata_r}));
axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) resp_fifo
(.reset(radio_rst),
.i_aclk(radio_clk), .i_tvalid(rmux_tvalid_r), .i_tready(rmux_tready_r), .i_tdata({rmux_tlast_r, rmux_tdata_r}),
.o_aclk(bus_clk), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .o_tdata({resp_tlast, resp_tdata}));
axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) rx_fifo
(.reset(radio_rst),
.i_aclk(radio_clk), .i_tvalid(rx_tvalid_r), .i_tready(rx_tready_r), .i_tdata({rx_tlast_r, rx_tdata_r}),
.o_aclk(bus_clk), .o_tvalid(rx_tvalid_int), .o_tready(rx_tready_int), .o_tdata({rx_tlast_int, rx_tdata_int}));
axi_packet_gate #(.WIDTH(64), .SIZE(SAMPLE_FIFO_SIZE), .USE_AS_BUFF(0)) buffer_whole_pkt
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata(rx_tdata_int), .i_tlast(rx_tlast_int), .i_terror(1'b0), .i_tvalid(rx_tvalid_int), .i_tready(rx_tready_int),
.o_tdata(rx_tdata), .o_tlast(rx_tlast), .o_tvalid(rx_tvalid), .o_tready(rx_tready));
///////////////////////////////////////////////////////////////////////////////////////
// Setting bus and controls
wire [63:0] ctrl_tdata_proc;
wire ctrl_tready_proc, ctrl_tvalid_proc;
wire ctrl_tlast_proc;
localparam SR_LOOPBACK = 8'd6;
localparam SR_SPI = 8'd8;
localparam SR_ATR = 8'd12; // thorugh 8'd18
localparam SR_TEST = 8'd21;
localparam SR_CODEC_IDLE = 8'd22;
localparam SR_READBACK = 8'd32;
localparam SR_TX_CTRL = 8'd64;
localparam SR_RX_CTRL = 8'd96;
localparam SR_TIME = 8'd128;
localparam SR_RX_FMT = 8'd136;
localparam SR_TX_FMT = 8'd138;
localparam SR_RX_DSP = 8'd144;
localparam SR_TX_DSP = 8'd184;
localparam SR_FP_GPIO = 8'd200; // thorugh 8'd206
localparam SR_USER_SR_BASE = 8'd253;
localparam SR_USER_RB_ADDR = 8'd255;
wire set_stb;
wire [7:0] set_addr;
wire [31:0] set_data;
wire [31:0] test_readback;
wire [9:0] fp_gpio_readback;
wire run_rx, run_tx;
wire rx_flow_ctrl_busy;
reg [63:0] rb_data;
wire [2:0] rb_addr;
wire [63:0] vita_time, vita_time_lastpps;
timekeeper #(.SR_TIME_HI(SR_TIME), .SR_TIME_LO(SR_TIME+1), .SR_TIME_CTRL(SR_TIME+2)) timekeeper
(.clk(radio_clk), .reset(radio_rst), .pps(pps), .sync_in(time_sync), .strobe(1'b1),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.vita_time(vita_time), .vita_time_lastpps(vita_time_lastpps),
.sync_out());
wire [31:0] debug_radio_ctrl_proc;
radio_ctrl_proc radio_ctrl_proc
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
.ctrl_tdata(ctrl_tdata_proc), .ctrl_tlast(ctrl_tlast_proc), .ctrl_tvalid(ctrl_tvalid_proc), .ctrl_tready(ctrl_tready_proc),
.resp_tdata(resp_tdata_r), .resp_tlast(resp_tlast_r), .resp_tvalid(resp_tvalid_r), .resp_tready(resp_tready_r),
.vita_time(vita_time),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.ready(1'b1), .readback(rb_data),
.debug(debug_radio_ctrl_proc));
reg [63:0] rb_data_user;
generate
if (USER_SETTINGS == 1) begin
wire set_stb_user;
wire [7:0] set_addr_user;
wire [31:0] set_data_user;
wire [7:0] rb_addr_user;
user_settings #(.BASE(SR_USER_SR_BASE)) user_settings
(.clk(radio_clk), .rst(radio_rst),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user));
setting_reg #(.my_addr(SR_USER_RB_ADDR), .awidth(8), .width(8)) user_rb_addr
(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(rb_addr_user), .changed());
// ----------------------------------
// Enter user settings registers here
// ----------------------------------
// Example code for 32-bit settings registers and 64-bit readback registers
//
// To test this, modify the *_core.v file for your specific USRP and set
// USER_SETTINGS=1 for the parameters for the radio_legacy instantiation.
//
// You can then use the get_user_settings_iface() like this:
//
// auto usrp = multi_usrp::make("type=b200,enable_user_regs");
// auto regs = usrp->get_user_settings_iface(0);
// regs->poke32(0, 0xCAFE);
// regs->poke32(4, 0xBEEF);
// std::cout << boost::format("0x%016X") % regs->peek64(0) << std::endl;
// wire [31:0] user_reg_0_value, user_reg_1_value;
setting_reg #(.my_addr(8'd0), .awidth(8), .width(32)) user_reg_0
(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb_user), .addr(set_addr_user), .in(set_data_user),
.out(user_reg_0_value), .changed());
setting_reg #(.my_addr(8'd1), .awidth(8), .width(32)) user_reg_1
(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb_user), .addr(set_addr_user), .in(set_data_user),
.out(user_reg_1_value), .changed());
always @* begin
case(rb_addr_user)
8'd0 : rb_data_user <= {user_reg_1_value[31:16], decoded_symbol_value, curr_sample_reg_value};
//8'd0 : rb_data_user <= {user_reg_1_value, user_reg_0_value};
default : rb_data_user <= 64'd0;
endcase
end
end else begin //for USER_SETTINGS == 1
always @* rb_data_user <= 64'd0;
end
endgenerate
always @*
case(rb_addr)
3'd0 : rb_data <= { 32'b0, test_readback };
3'd1 : rb_data <= vita_time;
3'd2 : rb_data <= vita_time_lastpps;
3'd3 : rb_data <= {tx, rx};
3'd4 : rb_data <= {54'h0,fp_gpio_readback};
3'd5 : rb_data <= {59'h0,rx_flow_ctrl_busy,ibs_state[3:0]}; // Monitor state of RX state machine.
// 3'd6 : rb_data <= <unused>;
3'd7 : rb_data <= rb_data_user;
default : rb_data <= 64'd0;
endcase // case (rb_addr)
//
// Sample VITA_TIME into the bus_clk domain for use by instrumentation.
//
wire [63:0] vita_time_b_int;
wire vita_time_b_valid;
axi_fifo_2clk #(.WIDTH(64), .SIZE(0)) vita_time_fifo
(.reset(radio_rst),
.i_aclk(radio_clk), .i_tvalid(1'b1), .i_tready(), .i_tdata(vita_time),
.o_aclk(bus_clk), .o_tvalid(vita_time_b_valid), .o_tready(1'b1), .o_tdata(vita_time_b_int));
always @(posedge bus_clk)
if (vita_time_b_valid)
vita_time_b <= vita_time_b_int;
// Set this register to loop TX data directly to RX data.
setting_reg #(.my_addr(SR_LOOPBACK), .awidth(8), .width(1)) sr_loopback
(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(loopback), .changed());
setting_reg #(.my_addr(SR_TEST), .awidth(8), .width(32)) sr_test
(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(test_readback), .changed());
setting_reg #(.my_addr(SR_CODEC_IDLE), .awidth(8), .width(32)) sr_codec_idle
(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(tx_idle), .changed());
setting_reg #(.my_addr(SR_READBACK), .awidth(8), .width(3)) sr_rdback
(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(rb_addr), .changed());
//The fe_atr pins driven by this module are always configured as outputs so default
//the DDR (data direction register) to be all ones (outputs) so that the drive direction
//these lines does not change during/after resets.
gpio_atr #(.BASE(SR_ATR), .WIDTH(32), .FAB_CTRL_EN(0), .DEFAULT_DDR(32'hFFFFFFFF), .DEFAULT_IDLE(32'h00000000)) fe_gpio_atr
(.clk(radio_clk),.reset(radio_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.rx(run_rx), .tx(run_tx),
.gpio_in(fe_gpio_in), .gpio_out(fe_gpio_out), .gpio_ddr(fe_gpio_ddr),
.gpio_out_fab(32'h00000000 /* no fabric control */), .gpio_sw_rb() );
generate
if (FP_GPIO != 0) begin: add_fp_gpio
gpio_atr #(.BASE(SR_FP_GPIO), .WIDTH(10), .FAB_CTRL_EN(0)) fp_gpio_atr
(.clk(radio_clk),.reset(radio_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.rx(run_rx), .tx(run_tx),
.gpio_in(fp_gpio_in), .gpio_out(fp_gpio_out), .gpio_ddr(fp_gpio_ddr),
.gpio_out_fab(10'h000 /* no fabric control */), .gpio_sw_rb(fp_gpio_readback));
end
endgenerate
///////////////////////////////////////////////////////////////////////////////////////
// Source flow control
generate
if (SOURCE_FLOW_CONTROL == 1) begin
localparam SID_PREFIX_CTRL = 2'd0;
localparam SID_PREFIX_FC = 2'd1;
wire [63:0] ctrl_tdata_fc;
wire ctrl_tready_fc, ctrl_tvalid_fc;
wire ctrl_tlast_fc;
wire [63:0] ctrl_hdr;
wire [1:0] ctrl_dest;
assign ctrl_dest = (ctrl_hdr[1:0] == SID_PREFIX_FC) ? 2'd1 : 2'd0;
axi_demux4 #(.ACTIVE_CHAN(4'b0011), .WIDTH(64), .BUFFER(1)) demux_proc_fc
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
.header(ctrl_hdr), .dest(ctrl_dest),
.i_tdata(ctrl_tdata_r), .i_tlast(ctrl_tlast_r), .i_tvalid(ctrl_tvalid_r), .i_tready(ctrl_tready_r), //Input
.o0_tdata(ctrl_tdata_proc), .o0_tlast(ctrl_tlast_proc), .o0_tvalid(ctrl_tvalid_proc), .o0_tready(ctrl_tready_proc), //Settings/Readback
.o1_tdata(ctrl_tdata_fc), .o1_tlast(ctrl_tlast_fc), .o1_tvalid(ctrl_tvalid_fc), .o1_tready(ctrl_tready_fc), //Flow control
.o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b0), //Unused
.o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0)); //Unused
source_flow_control_legacy #(.BASE(SR_RX_CTRL+6)) rx_sfc
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.fc_tdata(ctrl_tdata_fc), .fc_tlast(ctrl_tlast_fc), .fc_tvalid(ctrl_tvalid_fc), .fc_tready(ctrl_tready_fc), //Flow control In
.in_tdata(rx_prefc_tdata_r), .in_tlast(rx_prefc_tlast_r), .in_tvalid(rx_prefc_tvalid_r), .in_tready(rx_prefc_tready_r), //RX Input
.out_tdata(rx_postfc_tdata_r), .out_tlast(rx_postfc_tlast_r), .out_tvalid(rx_postfc_tvalid_r), .out_tready(rx_postfc_tready_r), //RX Output
.busy(rx_flow_ctrl_busy));
end else begin //for SOURCE_FLOW_CONTROL == 1
assign ctrl_tdata_proc = ctrl_tdata_r;
assign ctrl_tlast_proc = ctrl_tlast_r;
assign ctrl_tvalid_proc = ctrl_tvalid_r;
assign ctrl_tready_r = ctrl_tready_proc;
assign rx_postfc_tdata_r = rx_prefc_tdata_r;
assign rx_postfc_tlast_r = rx_prefc_tlast_r;
assign rx_postfc_tvalid_r = rx_prefc_tvalid_r;
assign rx_prefc_tready_r = rx_postfc_tready_r;
assign rx_flow_ctrl_busy = 1'b0;
end
endgenerate
// /////////////////////////////////////////////////////////////////////////////////
// TX Chain
wire [175:0] txsample_tdata;
wire txsample_tvalid, txsample_tready;
wire [31:0] sample_tx;
wire ack_or_error, packet_consumed;
wire [11:0] seqnum;
wire [63:0] error_code;
wire [31:0] sid;
wire [23:0] tx_fe_i, tx_fe_q;
wire [31:0] debug_tx_control;
always @(posedge radio_clk) begin
tx[31:16] <= (run_tx) ? tx_fe_i[23:8] : tx_idle[31:16];
tx[15:0] <= (run_tx) ? tx_fe_q[23:8] : tx_idle[15:0];
end
wire [63:0] tx_tdata_i; wire tx_tlast_i, tx_tvalid_i, tx_tready_i;
new_tx_deframer tx_deframer
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
.i_tdata(tx_tdata_i), .i_tlast(tx_tlast_i), .i_tvalid(tx_tvalid_i), .i_tready(tx_tready_i),
.sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready),
.debug());
new_tx_control #(.BASE(SR_TX_CTRL)) tx_control
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.vita_time(vita_time),
.ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
.seqnum(seqnum), .error_code(error_code), .sid(sid),
.sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready),
.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
.debug(debug_tx_control));
tx_responder #(.BASE(SR_TX_CTRL+2)) tx_responder
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
.seqnum(seqnum), .error_code(error_code), .sid(sid),
.vita_time(vita_time),
.o_tdata(txresp_tdata_r), .o_tlast(txresp_tlast_r), .o_tvalid(txresp_tvalid_r), .o_tready(txresp_tready_r));
wire [31:0] debug_duc_chain;
duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0), .WIDTH(24), .NEW_HB_INTERP(NEW_HB_INTERP),.DEVICE(DEVICE)) duc_chain
(.clk(radio_clk), .rst(radio_rst), .clr(1'b0),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
.debug(debug_duc_chain) );
`ifdef DELETE_FORMAT_CONVERSION
assign tx_tdata_i = tx_tdata_r;
assign tx_tlast_i = tx_tlast_r;
assign tx_tvalid_i = tx_tvalid_r;
assign tx_tready_r = tx_tready_i;
`else
chdr_xxxx_to_16sc_chain #(.BASE(SR_TX_FMT)) convert_xxxx_to_16sc
(.clk(radio_clk), .reset(radio_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.i_tdata(tx_tdata_r), .i_tlast(tx_tlast_r), .i_tvalid(tx_tvalid_r), .i_tready(tx_tready_r),
.o_tdata(tx_tdata_i), .o_tlast(tx_tlast_i), .o_tvalid(tx_tvalid_i), .o_tready(tx_tready_i),
.debug());
`endif // !`ifdef DELETE_FORMAT_CONVERSION
// /////////////////////////////////////////////////////////////////////////////////
// RX Chain
wire full, eob_rx;
wire strobe_rx;
wire [31:0] sample_rx;
wire [31:0] rx_sid;
wire [11:0] rx_seqnum;
wire [63:0] rx_tdata_i; wire rx_tlast_i, rx_tvalid_i, rx_tready_i;
wire [31:0] debug_rx_framer;
new_rx_framer #(.BASE(SR_RX_CTRL+4),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) new_rx_framer
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.vita_time(vita_time),
.strobe(strobe_rx), .sample(sample_rx), .run(run_rx), .eob(eob_rx), .full(full),
.sid(rx_sid), .seqnum(rx_seqnum),
.o_tdata(rx_tdata_i), .o_tlast(rx_tlast_i), .o_tvalid(rx_tvalid_i), .o_tready(rx_tready_i),
.debug(debug_rx_framer));
wire [31:0] debug_rx_control;
new_rx_control #(.BASE(SR_RX_CTRL)) new_rx_control
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.vita_time(vita_time),
.strobe(strobe_rx), .run(run_rx), .eob(eob_rx), .full(full),
.sid(rx_sid), .seqnum(rx_seqnum),
.err_tdata(rx_err_tdata_r), .err_tlast(rx_err_tlast_r), .err_tvalid(rx_err_tvalid_r), .err_tready(rx_err_tready_r),
.ibs_state(ibs_state),
.debug(debug_rx_control));
wire [31:0] debug_ddc_chain;
// Digital Loopback TX -> RX (Pipeline immediately inside rx_frontend).
wire [31:0] rx_fe = loopback ? tx : rx;
ddc_chain #(.BASE(SR_RX_DSP), .DSPNO(0), .WIDTH(24), .NEW_HB_DECIM(NEW_HB_DECIM), .DEVICE(DEVICE)) ddc_chain
(.clk(radio_clk), .rst(radio_rst), .clr(1'b0),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.rx_fe_i({rx_fe[31:16],8'd0}),.rx_fe_q({rx_fe[15:0],8'd0}),
.sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
.debug(debug_ddc_chain) );
decoder_top decoder_top
(.clock(strobe_rx),
.enable_counter(1'b1),
.ref_in(32'd30), // Hard-coded now, we will be using the user_reg_0_value to read the 'sample_rx' via the user registers
.data_in(sample_rx),
.decoded_symbol(decoded_symbol_value) );
always @(posedge strobe_rx) begin
curr_sample_reg <= sample_rx; // Latch the sample at strobe_rx signal, we will then read the user register via the UHD
end
assign curr_sample_reg_value = curr_sample_reg;
`ifdef DELETE_FORMAT_CONVERSION
assign rx_prefc_tdata_r = rx_tdata_i;
assign rx_prefc_tlast_r = rx_tlast_i;
assign rx_prefc_tvalid_r = rx_tvalid_i;
assign rx_tready_i = rx_prefc_tready_r;
`else
chdr_16sc_to_xxxx_chain #(.BASE(SR_RX_FMT)) convert_16sc_to_xxxx
(.clk(radio_clk), .reset(radio_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.i_tdata(rx_tdata_i), .i_tlast(rx_tlast_i), .i_tvalid(rx_tvalid_i), .i_tready(rx_tready_i),
.o_tdata(rx_prefc_tdata_r), .o_tlast(rx_prefc_tlast_r), .o_tvalid(rx_prefc_tvalid_r), .o_tready(rx_prefc_tready_r),
.debug());
`endif
// /////////////////////////////////////////////////////////////////////////////////
// RX Channel Muxing
axi_mux4 #(.PRIO(1), .WIDTH(64), .BUFFER(1)) rx_mux
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
.i0_tdata(rx_postfc_tdata_r), .i0_tlast(rx_postfc_tlast_r), .i0_tvalid(rx_postfc_tvalid_r), .i0_tready(rx_postfc_tready_r),
.i1_tdata(rx_err_tdata_r), .i1_tlast(rx_err_tlast_r), .i1_tvalid(rx_err_tvalid_r), .i1_tready(rx_err_tready_r),
.i2_tdata(64'h0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
.i3_tdata(64'h0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
.o_tdata(rx_tdata_r), .o_tlast(rx_tlast_r), .o_tvalid(rx_tvalid_r), .o_tready(rx_tready_r));
// /////////////////////////////////////////////////////////////////////////////////
// Response Channel Muxing
axi_mux4 #(.PRIO(0), .WIDTH(64)) response_mux
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
.i0_tdata(txresp_tdata_r), .i0_tlast(txresp_tlast_r), .i0_tvalid(txresp_tvalid_r), .i0_tready(txresp_tready_r),
.i1_tdata(resp_tdata_r), .i1_tlast(resp_tlast_r), .i1_tvalid(resp_tvalid_r), .i1_tready(resp_tready_r),
.i2_tdata(64'h0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
.i3_tdata(64'h0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
.o_tdata(rmux_tdata_r), .o_tlast(rmux_tlast_r), .o_tvalid(rmux_tvalid_r), .o_tready(rmux_tready_r));
/*******************************************************************
* Debug only logic below here.
******************************************************************/
assign debug = 0;
endmodule // radio_legacy
20c20
< parameter USER_SETTINGS = 0,
---
> parameter USER_SETTINGS = 1,
38a39,46
> //
> ////////////////////////////////////////////////////////////////////////////////
> // Interconnects for the user defined registers
>
> wire [31:0] user_reg_0_value, user_reg_1_value, curr_sample_reg_value;
> wire [15:0] decoded_symbol_value;
>
> reg [31:0] curr_sample_reg;
>
200c208
< wire [31:0] user_reg_0_value, user_reg_1_value;
---
> // wire [31:0] user_reg_0_value, user_reg_1_value;
212c220,221
< 8'd0 : rb_data_user <= {user_reg_1_value, user_reg_0_value};
---
> 8'd0 : rb_data_user <= {user_reg_1_value[31:16],
> decoded_symbol_value, curr_sample_reg_value};
> //8'd0 : rb_data_user <= {user_reg_1_value, user_reg_0_value};
451a461,474
>
> decoder_top decoder_top
> (.clock(strobe_rx),
> .enable_counter(1'b1),
> .ref_in(32'd30), // Hard-coded now, we
> will be using the user_reg_0_value to read the 'sample_rx' via the user
> registers
> .data_in(sample_rx),
> .decoded_symbol(decoded_symbol_value) );
>
> always @(posedge strobe_rx) begin
> curr_sample_reg <= sample_rx; // Latch the sample at
> strobe_rx signal, we will then read the user register via the UHD
> end
>
> assign curr_sample_reg_value = curr_sample_reg;
>
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