On 03/19/2020 08:09 PM, Neel Pandeya via USRP-users wrote:
Which 10 Gbps network card are you using?
--Neel Pandeya
Also, are you certain that your IP stack is actually routing to one of
those two cards?
On Thu, 19 Mar 2020 at 10:50, Carmichael, Ryan via USRP-users
<[email protected] <mailto:[email protected]>> wrote:
I had an application running with 3.11.1 libraries and and my X310
corresponding firmware. After building and installing 3.15.0 on my
system and flashing the X310, everything seemed okay.
However, we now get this error when starting up:
*[WARNING] [X300] You requested a send frame size of (9000) but
your NIC's max frame size is (8000).Please verify your NIC's MTU
setting using 'ip link' or set the send_frame_size argument
appropriately.UHD will use the auto-detected max frame size for
this connection.*
*
*
And when we start to transmit, odd errors like this show up (what
is 'this can cause 27.0464' trying to tell me?):
*[WARNING] [MULTI_USRP] The total sum of rates (66.666667 MSps on
1 channels) exceeds the maximum capacity of the connection
(overflows (O) MSps).
This can cause 27.0464.*
I'm using 10Gb NICs that again, worked fine with 3.11. The MTUs
are set to 9000 (I've also tried 9001, 9100, nothing seems to
change the warning).
*ip link*
*6: enp13s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 9000 qdisc mq
state UP mode DEFAULT group default qlen 1000
link/ether f8:f2:1e:42:e1:d4 brd ff:ff:ff:ff:ff:ff
7: enp13s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 9000 qdisc mq
state UP mode DEFAULT group default qlen 1000
link/ether f8:f2:1e:42:e1:d5 brd ff:ff:ff:ff:ff:ff*
*
*
The usrp_probe output is below. Any ideas on what is happening?
*uhd_usrp_probe --args="addr=192.168.30.2"
[INFO] [UHD] linux; GNU C++ version 4.8.5 20150623 (Red Hat
4.8.5-39); Boost_106700; UHD_3.15.0.0-7-g8d228dbe
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Maximum frame size: 8000 bytes.
[INFO] [X300] Radio 1x clock: 200 MHz
[INFO] [GPS] No GPSDO found
[INFO] [0/DmaFIFO_0] Initializing block control (NOC ID:
0xF1F0D00000000000)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1321 MB/s)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1300 MB/s)
[INFO] [0/Radio_0] Initializing block control (NOC ID:
0x12AD100000000001)
[INFO] [0/Radio_1] Initializing block control (NOC ID:
0x12AD100000000001)
[INFO] [0/DDC_0] Initializing block control (NOC ID:
0xDDC0000000000000)
[INFO] [0/DDC_1] Initializing block control (NOC ID:
0xDDC0000000000000)
[INFO] [0/DUC_0] Initializing block control (NOC ID:
0xD0C0000000000000)
[INFO] [0/DUC_1] Initializing block control (NOC ID:
0xD0C0000000000000)
_____________________________________________________
/
| Device: X-Series Device
| _____________________________________________________
| /
| | Mboard: X310
| | revision: 11
| | revision_compat: 7
| | product: 30818
| | mac-addr0: 00:80:2f:24:d2:a9
| | mac-addr1: 00:80:2f:24:d2:aa
| | gateway: 192.168.10.1
| | ip-addr0: 192.168.10.2
| | subnet0: 255.255.255.0
| | ip-addr1: 192.168.20.2
| | subnet1: 255.255.255.0
| | ip-addr2: 192.168.30.2
| | subnet2: 255.255.255.0
| | ip-addr3: 192.168.40.2
| | subnet3: 255.255.255.0
| | serial: 318D6DF
| | FW Version: 6.0
| | FPGA Version: 36.0
| | FPGA git hash: 9ba275d
| | RFNoC capable: Yes
| |
| | Time sources: internal, external, gpsdo
| | Clock sources: internal, external, gpsdo
| | Sensors: ref_locked
| | _____________________________________________________
| | /
| | | RX Dboard: A
| | | ID: UBX-160 v2 (0x007e)
| | | Serial: 3185BEE
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: UBX RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step
0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: A
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | RX Dboard: B
| | | ID: UBX-160 v2 (0x007e)
| | | Serial: 3185CA1
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: UBX RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step
0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: B
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | TX Dboard: A
| | | ID: UBX-160 v2 (0x007d)
| | | Serial: 3185BEE
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: UBX TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step
0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: A
| | | | Name: ad9146
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | TX Dboard: B
| | | ID: UBX-160 v2 (0x007d)
| | | Serial: 3185CA1
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: UBX TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step
0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: B
| | | | Name: ad9146
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | RFNoC blocks on this device:
| | |
| | | * DmaFIFO_0
| | | * Radio_0
| | | * Radio_1
| | | * DDC_0
| | | * DDC_1
| | | * DUC_0
| | | * DUC_1*
Thanks,
Ryan
/
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