Hi Ivan, When you build a custom RFNoC image for the E310 using uhd_image_builder, only the radio core RFNoC block is included automatically. If you did not specifically include a DDC or DUC block, then they were not included in the build. The E310 is based on the Zynq 7020 and has limited resources. The Fosphor example by itself uses up almost all of the device's FPGA resources and adding another RFNoC block without modifying the design is not possible.
One experiment you could try is modifying line 11 in noc_block_fosphor.v to increase the MTU size from 11 to 13 or 14. That may allow you to no longer need the AXI FIFO RFNoC blocks. Without those blocks, you might be able to fit in the FIR filter RFNoC block. Jonathon On Sun, May 10, 2020 at 7:10 AM Ivan Zahartchuk via USRP-users < [email protected]> wrote: > Hello. I want to create an image of fosphor, window, fft, 2x AXI FIFOs, > FIR for USRP E310. I need to change the spectral bandwidth. But with the > samp_rate parameter this does not work out very well. Therefore, I want to > use the FIR filter for these purposes, but when building the bit file, I do > not have enough space on the FPGA. Therefore, I decided to turn off the DDC > and DUC blocks, but I don’t know how to do it. I would be grateful for any > information. > _______________________________________________ > USRP-users mailing list > [email protected] > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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