ok. I'm not sure if there is an upper limit, but I believe you should be able to have 4 ports because there are 4 ports in the DmaFIFO on the N310.
On Thu, May 21, 2020 at 4:21 PM Carlos Alberto Ruiz Naranjo < [email protected]> wrote: > Hi Rob, > > I'm using UHD-3.15.LTS and I have developed a custom DUC with N inputs and > 1 output. I have done the same with the DDC (1:N) and it works fine. But > with the DUC I have the problem with the DMA_FIFO, I need one DMA_FIFO > channel per DUC channel. I have thought about some solutions and I would > like to know which would be the best or if they are possible before I > started developing: > > - Increase the DMA_FIFO ports: from 2 to 4. > - Add another DMA_FIFO. > - Use FIFO_LOOPBACK with large size. > > My graph is: DMA_FIFO(N:N) -> (N:1) DUC -> (1) Radio > > Thank you :) > > > > > El jue., 21 may. 2020 a las 21:13, Rob Kossler (<[email protected]>) > escribió: > >> Hi Carlos, >> I don't quite understand. Which version of UHD are you using? For the >> UHD 3.15 and earlier, I thought that the typical configuration was indeed >> host->DmaFIFO->DUC->Radio as you were hoping for. For the current master, >> I noticed that the DmaFIFO is not included in the statically routed FPGA >> image. But, aside from the master branch, the DmaFIFO should have 2 ports >> such that you can connect to two DUC blocks. >> Rob >> >> On Thu, May 21, 2020 at 2:34 PM Brian Padalino via USRP-users < >> [email protected]> wrote: >> >>> On Thu, May 21, 2020 at 2:25 PM Carlos Alberto Ruiz Naranjo < >>> [email protected]> wrote: >>> >>>> Thank you for the response Brian :) >>>> >>>> The throughput is about 11MSamples. >>>> What about to use the AXI_FIFO_LOOPBACK? >>>> >>> >>> No idea about that. Someone else will have to weigh in. >>> >>> Good luck! >>> >>> Brian >>> >>>> _______________________________________________ >>> USRP-users mailing list >>> [email protected] >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>
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