On 05/23/2020 08:36 PM, Manav Kohli via USRP-users wrote:
Dear Sam,
Your shot in the dark hit the bullseye. At 25 MHz, this problem goes
away entirely. Will have to work around the limitation at 20 MHz BW in
the future.
Thank you very much!
Manav
Here's a good article on CIC filter design in both interpolators and
decimators.
https://www.dsprelated.com/showarticle/1337.php
The basic issue is that all CIC filters require some compensation after
the filter. But FPGA real-estate being what it is, the post-compensation
filters in the N210/N200 are all decimate-by-two FIR filters. Which
means they don't get switched "in circuit" for odd decimation factors.
A sample-rate of 20Msps with a 100Msps sample clock means decimation
by 5, which means you're just getting the CIC decimator response
without the compensating decimate-by-two effect of the FIR half-band
filter.
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