Hi,
In UHD you find :
void set_time_next_pps(const uhd::time_spec_t &time){
const uint64_t ticks = time.to_ticks(_tick_rate);
_iface->poke32(REG_TIME64_TICKS_LO, uint32_t(ticks >> 0));
_iface->poke32(REG_TIME64_IMM, FLAG_TIME64_LATCH_NEXT_PPS);
_iface->poke32(REG_TIME64_TICKS_HI, uint32_t(ticks >> 32));
//latches all 3
}
with seemingly the write of the 'HI' part being the trigger point.
In the FPGA code (timekeeper.v) you have :
setting_reg #(.my_addr(SR_TIME_CTRL), .width(3)) sr_ctrl
(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out({set_time_sync, set_time_pps, set_time_now}), .changed(cmd_trigger));
So the 'cmd_trigger' that synchronizes the action is on the 'CTRL'
(aka REG_TIME64_IMM) register and not on the hi part of the time.
TBH I'm not even sure how set_time_now works at all ... it has the
same issue and AFAICT it would always end up using the previous value
of the 'hi' register...
Am I missing something here ?
Cheers,
Sylvain Munaut
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