Hi everyone, I'm working on usrp x310 . I create my own version of the replay block . I almost didn't change anything in the 2 state machines in the axi_replay.v . everything worked fine but then i saw in the chipscope that my replay block got data after 110 clks. (although the read ctrl ports indicate that the ddr start processing my read request ) Is there any reason it takes 110clks to get the first data from a burst ? How can I lower this high latency ?
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