Ben, u-boot and kernel builds are part of the filesystem build. You'll want to build upon our version of the kernel anyway (i.e. include our patches). The fsbl is exported from Vivado, if you want to change that it's a bit more effort. I suggest getting familiar with the OE build first. Phil's links will help.
Cheers, M On Tue, 13 Oct 2020, 09:35 Turner, Ben via USRP-users, < [email protected]> wrote: > Martin, > > Thank you for your reply. > > Unfortunately simply modifying the filesystem is not enough - I need to be > able to customise u-boot and the kernel. As it is a Xilinx based system I > was under the impression that PetaLinux was the sensible approach and I > seem to be most of the way there, with the exception being this FSBL error > and the generated u-boot not outputting to the serial terminal. > > By saying you are unable to help with PetaLinux issues, are you implying > you are able to help with another mechanism for generating the FSBL, u-boot > and kernel? Or are you stating that you flat out refuse to help with issues > related to generating these binaries? > > Regards, > > Ben > > > > *From:* USRP-users <[email protected]> *On Behalf Of *Martin > Braun via USRP-users > *Sent:* 12 October 2020 09:59 > *Cc:* [email protected] > *Subject:* Re: [USRP-users] Ettus E320 & PetaLinux > > > > Ben, > > > > we can't provide you with PetaLinux support, but you can rebuild our > OE-Based filesystems. For novice OpenEmbedded users, we provide a Docker > image (here's a link from the E320 manual: > https://github.com/EttusResearch/ettus-docker/blob/master/oe-build/README.md), > and if you're more of an expert, you can go straight to our manifests ( > https://github.com/EttusResearch/oe-manifests) which contain references > to all the layers used to build our filesystems. > > > > A bunch of USRP users build custom filesystems (with their own software > etc.) and use this workflow. > > > > Cheers, > > M > > > > > > > > Follow Us: LinkedIn <http://www.linkedin.com/company/roke-manor-research> > | Twitter <https://twitter.com/rokemanor> | Facebook > <https://www.facebook.com/rokemanor> > > Roke Manor Research Limited, Romsey, Hampshire, SO51 0ZN, United Kingdom. > Part of the Chemring Group. Registered in England & Wales. Registered No: > 00267550. The information contained in this e-mail and any attachments is > proprietary to Roke Manor Research Limited and must not be passed to any > third party without permission. This communication is for information only > and shall not create or change any contractual relationship. > www.roke.co.uk > <http://www.roke.co.uk/?utm_source=Roke&utm_medium=Email&utm_content=Company%20Signature&utm_campaign=Roke> > ------------------------------ > > On Mon, Oct 12, 2020 at 10:43 AM Turner, Ben via USRP-users < > [email protected]> wrote: > > I am attempting to build PetaLinux targeting the E320. As there is no BSP > (that I can find) for the E320, I have attempted to generate a hardware > description file from the Vivado project that can be created from the Ettus > FPGA github repository <https://github.com/EttusResearch/fpga>. > > > > I successfully created the Vivado project by running make E320_1G GUI=1, > ran synthesis and implementation and then exported the .hdf. I then > configured the PetaLinux project: > > > > petalinux-config –get-hw-description=<path_to_.hdf> > > > > And attempted to build it: > > > > petalinux-build > > > > It is during this build stage that I get the following error: > > > > NOTE: Executing RunQueue Tasks > > ERROR: fsbl-2018.3+gitAUTOINC+56f3da2afb-r0 do_configure: Function failed: > do_configure (log file is located at > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/temp/log.do_configure.18082) > > ERROR: Logfile of failure stored in: > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/temp/log.do_configure.18082 > > Log data follows: > > | DEBUG: Executing shell function do_configure > > | MISC_ARG is -yamlconf > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/fsbl.yaml > > | APP_ARG is -app "Zynq FSBL" > > | Using xsct from: > /opt/Xilinx/PetaLinux/2018.3/tools/xsct/SDK/2018.3/bin/xsct > > | cmd is: xsct -sdx -nodisp > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/app.tcl > -ws > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/build > -pname fsbl -rp > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/git > -processor ps7_cortexa9_0 -hdf > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/deploy/images/plnx-zynq7/Xilinx-plnx-zynq7.hdf > -arch 32 -app "Zynq FSBL" -yamlconf > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/fsbl.yaml > > | INFO: [Hsi 55-1698] elapsed time for repository loading 0 seconds > > | Opening the hardware design, this may take few seconds. > > | expected integer but got "" > > | ERROR: [Hsi 55-1545] Problem running tcl command > ::sw_scugic_v3_10::generate : expected integer but got "" > > | while executing > > | "format "#define XPAR_FABRIC_%s_%s_INTR %d$uSuffix" [string toupper > $ip_name] [string toupper $port_name] $port_intr_id" > > | ("foreach" body line 86) > > | invoked from within > > | "foreach periph $periphs { > > | > > | # get the gic mode information > > | set scugic_mode [common::get_property CONFIG.C_IRQ_F2P_MODE > $periph] > > | > > | ..." > > | (procedure "xdefine_gic_params" line 30) > > | invoked from within > > | "xdefine_gic_params $drv_handle" > > | (procedure "::sw_scugic_v3_10::generate" line 10) > > | invoked from within > > | "::sw_scugic_v3_10::generate ps7_scugic_0" > > | ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate() > > | Failed to generate the platform. > > | Reason: Failed to generate the bsp sources for domain.fsbl_domain > > | while executing > > | "builtin_platform -generate quick" > > | (procedure "platform" line 221) > > | invoked from within > > | "platform generate -quick" > > | invoked from within > > | "if { $params(ws) ne "" } { > > | #Local Work Space available > > | if { $params(pname) ne "" } { > > | # hwpname/bspname is empty then default it > to pname+_hwproj/b..." > > | (file > "/home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/app.tcl" > line 139) > > | WARNING: > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/temp/run.do_configure.18082:1 > exit 1 from 'xsct -sdx -nodisp > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/app.tcl > -ws > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/build > -pname fsbl -rp > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/git > -processor ps7_cortexa9_0 -hdf > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/deploy/images/plnx-zynq7/Xilinx-plnx-zynq7.hdf > -arch 32 -app "Zynq FSBL" -yamlconf > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/fsbl.yaml' > > | ERROR: Function failed: do_configure (log file is located at > /home/devel/Projects/e320/plnx-2018.3-e320/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/temp/log.do_configure.18082) > > ERROR: Task > (/opt/Xilinx/PetaLinux/2018.3/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_configure) > failed with exit code '1' > > NOTE: Tasks Summary: Attempted 2999 tasks of which 2234 didn't need to be > rerun and 1 failed. > > > > Summary: 1 task failed: > > > /opt/Xilinx/PetaLinux/2018.3/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb: > do_configure > > Summary: There was 1 ERROR message shown, returning a non-zero exit code. > > ERROR: Failed to build project > > > > The build fails when attempting to configure the first stage bootloader. > > > > I have also attempted to create an FSBL directly through the SDK however > that gives a very similar error: > > > > 9:43:04 INFO : Registering command handlers for SDK TCF services > > 09:43:05 INFO : Launching XSCT server: xsct -n -interactive > /home/devel/Projects/e320/fsbl-2018.3/temp_xsdb_launch_script.tcl > > 09:43:10 INFO : XSCT server has started successfully. > > 09:43:10 INFO : Successfully done setting XSCT server connection channel > > 09:43:11 INFO : Successfully done setting SDK workspace > > 09:44:54 INFO : Project 'fsbl' created. You can now create BSPs and > application projects targeting this hardware platform. > > 09:45:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1545] Problem running tcl > command ::sw_scugic_v3_10::generate : expected integer but got "" > > while executing > > "format "#define XPAR_FABRIC_%s_%s_INTR %d$uSuffix" [string toupper > $ip_name] [string toupper $port_name] $port_intr_id" > > ("foreach" body line 86) > > invoked from within > > "foreach periph $periphs { > > > > # get the gic mode information > > set scugic_mode [common::get_property CONFIG.C_IRQ_F2P_MODE > $periph] > > > > ..." > > (procedure "xdefine_gic_params" line 30) > > invoked from within > > "xdefine_gic_params $drv_handle" > > (procedure "::sw_scugic_v3_10::generate" line 10) > > invoked from within > > "::sw_scugic_v3_10::generate ps7_scugic_0" > > > > 09:45:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1442] Error(s) while running > TCL procedure generate() > > > > 09:45:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1450] Error: running > generate_bsp. > > > > 09:45:21 ERROR : Error generating bsp sources: Failed in generating sources > > > > I have not changed anything in the default vivado project that is > generated. > > > > I have circumvented building the FSBL for the time being by disabling it > in the petalinux-config top level menu, however I would ideally like to be > able to build it! > > > > I am very new to FPGA development and this is my first foray into using > the Xilinx tools and PetaLinux, so any help would be appreciated. > > > > Thanks, > > > > Ben > > Follow Us: LinkedIn <http://www.linkedin.com/company/roke-manor-research> > | Twitter <https://twitter.com/rokemanor> | Facebook > <https://www.facebook.com/rokemanor> > > Roke Manor Research Limited, Romsey, Hampshire, SO51 0ZN, United Kingdom. > Part of the Chemring Group. Registered in England & Wales. Registered No: > 00267550. The information contained in this e-mail and any attachments is > proprietary to Roke Manor Research Limited and must not be passed to any > third party without permission. This communication is for information only > and shall not create or change any contractual relationship. > www.roke.co.uk > <http://www.roke.co.uk/?utm_source=Roke&utm_medium=Email&utm_content=Company%20Signature&utm_campaign=Roke> > ------------------------------ > > _______________________________________________ > USRP-users mailing list > [email protected] > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > _______________________________________________ > USRP-users mailing list > [email protected] > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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