I'd like to pass metadata over the dataplane using the available space in the
CHDR header. However, I cannot find an easy way to do this using UHD3.15.
I've identified two possible approaches but I'm not sure either will work:
(1) Set AXI_Wrapper (Simple_Mode =0) to require user provided CHDR header. It's
unclear how to provide the header, and if this can be modified quickly.
(2) Expose the AXI-Stream CHDR interface the way UHD4.0 does it:
In UHD4.0 the verilog_image_builder.py includes the options to expose HDL
interface:
o Definition: Which HDL interface to expose
o Options: “AXI-Stream CHDR” (axis_chdr), “AXI-Stream Payload Context”
(axis_pyld_ctxt), or “AXI-Stream Data” (axis_data)
If Option (2) is the recommended, can I just copy the code from
verilog_image_builder.py TEMPLATE such as below, or were other changes made to
make it incompatible with 3.15?
%if config['data']['fpga_iface'] == "axis_pyld_ctxt":
assign axis_data_clk = ${config['data']['clk_domain']}_clk;
assign axis_data_rst = ${config['data']['clk_domain']}_rst;
<%include file="/modules/axis_pyld_ctxt_modules_template.mako"/>
Thanks,
Jeff
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