HI Maria, Rfnocmodtool does not support multiple inputs / outputs. You'll need to edit the generated yaml file and use it with the utility rfnoc_create_verilog to generate the block and noc shell. See https://kb.ettus.com/RFNoC_4_Migration_Guide#Generating_a_Custom_Noc_Shell. To edit the yaml file, you can refer to the RFNoC specification ( https://files.ettus.com/app_notes/RFNoC_Specification.pdf) or look at an existing RFNoC block's yaml file that supports multiple ports such as the FIR filter block (uhd/host/include/uhd/rfnoc/blocks/fir_filter.yml).
Also, as you've noticed, the generated yaml file has the wrong interface, "fpga_iface: axis_data" should be "fpga_iface: axis_pyld_ctxt". That is a known issue that is in the pipeline to be fixed. Jonathon On Wed, Jan 20, 2021 at 8:18 AM Maria Muñoz via USRP-users < [email protected]> wrote: > Hi all, > > Is it possible to automatically create an rfnoc_block schema with, for > example, 2 inputs and 2 outputs payload stream packets as in the addsub > blockdata using rfnocmodtool? > I can generate it using rfnoc_create_verilog.py through a block.yml file > following the steps in : > https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0#Generating_Your_Block_Using_the_ModTool > But I don't know the steps to do that using rfnocmodtool, it always > generates a 1 input, 1 output block with axis_pyload_ctxt interface even > though the block.yml generated in block folder has axis_data interface: > > > > > > > > > *schema: rfnoc_modtool_argsmodule_name: multinoutversion: > 1.0rfnoc_version: 1.0chdr_width: 64noc_id: 0x4321makefile_srcs: > "/home/usr/rfnoc/src/gr-ettus/rfnoc-prueba/rfnoc/fpga/rfnoc_block_multinout/Makefile.srcs"* > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > *clocks: - name: rfnoc_chdr freq: "[]" - name: rfnoc_ctrl freq: > "[]" - name: ce freq: "[]"control: sw_iface: nocscript fpga_iface: > ctrlport interface_direction: slave fifo_depth: 32 clk_domain: ce > ctrlport: byte_mode: False timed: False has_status: Falsedata: > fpga_iface: axis_data clk_domain: ce inputs: in: item_width: 32 > nipc: 1 info_fifo_depth: 32 payload_fifo_depth: 32 > format: int32 mdata_sig: ~ outputs: out: item_width: 32 > nipc: 1 info_fifo_depth: 32 payload_fifo_depth: 32 format: > int32* > * mdata_sig: ~* > > Can I modify this file and somehow reload the files generated in the first > attempt or is there other way to do what I want? > > Kind Regards, > > Maria > _______________________________________________ > USRP-users mailing list > [email protected] > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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