Hi, I was searching for a way to interface the control interface of a Simulink HDL Coder IP Core to the RFNoC Shell.
Normally i would expose all control registers over an AXI4-Lite interface. I took a look at the rfnoc_core_addsub, since it uses Xilinx HLS, but that example does not expose control registers at all, thereby avoiding this problem. I guess the question is, how i would i tackle this connection from the CtrlPort of the NoC Shell to AXI4-Lite? A nudge in the right direction would be highly appreciated! Regards, Julian Daube PS: I would like to integrated said core into the UHD 4.0 framework and build images for the X310, if this of relevance. Since it will be a FIR Filter similar to the axi_filter block, i would like to avoid using a parallel configuration bus.
_______________________________________________ USRP-users mailing list [email protected] http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
