Hi Julian, You should not need to adjust the ce_clk rate. The AXI Stream ready/valid handshake allows you to clock your logic at a higher rate, but still have the correct average throughput. If your block consumes the incoming samples faster than the DDC output sample rate, your block's logic will just wait until the next sample is available (i.e. it will wait for the AXI stream output from noc_shell to assert tvalid).
Jonathon On Thu, Apr 15, 2021 at 3:50 PM <[email protected]> wrote: > Hi all, > > > I am designing a custom RFNoC block based on RFNoC4 video which is using > the ce_clk 200MHz, please correct me if I am wrong. > > That RFNoC block will be instantiated twice, one in the RX side and the > other in the TX (the core yaml file has both instances). The receiver chain > will look like this, something similar in the TX side but the other way > around. > > > radio -> ddc -> rfnoc custom block ->rx_streamer-> USRP (host side). > > > I am planning to use an *User Register* to let our custom RFNOC block the > data rate we want to set in the DDC and DUC, and then use a prescaler to > change the rate of ce_clk matching the digital converters rate. I wonder if > this is the right approach or maybe I am missing any caveat I need to look. > > > Thanks > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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