Good morning Julian. To solve this problem I would follow two approaches based on what I want to know.
1) I want to know the total number o samples handled by my block: I would use just a counter that increment using the input valid signal from the axi_wrapper. As clock for this counter I would use ce_clk. 2) I want to know the actual number of samples in my block: I would use two counter. The first is the same I would use in case 1, while the second is a counter that increment on my valid signal (from my logic to the axi_wrapper). BTW the ce_clk (at least in X310 devices and as far as I can understand reading the FPGA code) is not exactly 200MHz, but it should be a bit more (if I remember correctly bout 214MHz). I hope this considerations can be of some help Best Paolo _______________________________________________ USRP-users mailing list -- [email protected] To unsubscribe send an email to [email protected]
