Hello, It is not a limitation of the AD9361 chip but rather of its implementation. The AD9361 can be implemented using a CMOS data interface which limits the data rate as described. It can also be implemented with an LVDS data interface that allows full rate of 61.44 Mbps for both Rx channels. Since the chosen implementation for the E310 (I guess from the answers, that it is the same for the E320 as well, although curious) is CMOS data interface hence the data rate limitation.
I know my answer does not help you because you can't change the hardware design but I thought you would like to know. Regards, Ofer Saferman On Sun, May 9, 2021 at 10:30 AM <[email protected]> wrote: > Send USRP-users mailing list submissions to > [email protected] > > To subscribe or unsubscribe via email, send a message with subject or > body 'help' to > [email protected] > > You can reach the person managing the list at > [email protected] > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of USRP-users digest..."Today's Topics: > > 1. Re: E310 / E320 high bandwith / high datarate two channel RX capture > (Martin) > > > > ---------- Forwarded message ---------- > From: Martin <[email protected]> > To: Marcus D Leech <[email protected]>, Rob Kossler <[email protected] > > > Cc: [email protected] > Bcc: > Date: Sat, 8 May 2021 12:13:04 +0200 > Subject: [USRP-users] Re: E310 / E320 high bandwith / high datarate two > channel RX capture > So it's a hardware limitation of the AD9361 chip? > That is very unfortunate. > > We were also looking at an option to build our own device based on a > AD9361 + some Zync FPGA/ARM processor. > But if it is a hardware limitation of the AD9361 then that would not > work either. > > Thanks for the info. > > Best regards, > Martin > > > On 07-05-2021 17:23, Marcus D Leech wrote: > > The E320 uses the same RFFE as the E310 so would have the same bandwidth > > restrictions. > > > > Sent from my iPhone > > > >> On May 7, 2021, at 10:50 AM, Marcus D Leech <[email protected]> > >> wrote: > >> > >> Indeed the E310 RFFE chip has clocking restrictions so that two > >> channels are limited to less than 32MHz. > >> > >> I’m not certain about the E320. > >> > >> Sent from my iPhone > >> > >>> On May 7, 2021, at 10:45 AM, Rob Kossler <[email protected]> wrote: > >>> > >>> > >>> Hi Martin, > >>> I am concerned that these devices, E3xx, cannot handle 2 channels at > >>> 56 MS/s (or 61MS/s). My understanding (but I am not 100% sure) is > >>> that these devices can handle 1 channel at those rates, but that the > >>> max rate for 2 channels is 30.72 MS/s. > >>> Rob > >>> > >>> On Fri, May 7, 2021 at 9:41 AM Martin > >>> <[email protected] > >>> <mailto:[email protected]>> wrote: > >>> > >>> Hi, > >>> > >>> Do you have experience with high bandwidth capture on E310 or E320? > >>> > >>> We want to use an E310 or E320 for 56 MSPS (or 61.44 MSPS) dual > >>> channel > >>> RX captures. > >>> We want to capture into a circular buffer and after a certain > signal > >>> signal level is observed set a time to stop capturing after 0.3 > >>> seconds. > >>> So we only use the last 0.3 second of captured data. > >>> > >>> We are thinking of using a E320. This has a high speed SFP+ 10 > >>> gbit port. > >>> Can it stream 2 channel 56 MSPS data to a host-PC continuously to a > >>> host-PC? Or is the ARM processor a bottleneck, like on the E310, > >>> which > >>> seems to be limited to max 16MSPS due to the limited arm > >>> processor speed. > >>> And can it stream that fast with its default FPGA firmware image, > so > >>> there would be no need for RFNoc work and expensive Vivado license. > >>> > >>> And if we do need the Xilinx vivado license. Which version do we > >>> need? > >>> > >>> Alternatively we could try to use the E310 which has a smaller > >>> FPGA that > >>> is supported by the free webpack of vivado. > >>> Because it does not have a 10 gbit ethernet we would have to > >>> capture to > >>> memory. > >>> I have read that the E310 arm processing is not able to keep up > with > >>> more then 16 MSPS captures. So just streaming to the ARM memory > >>> in the > >>> E310 would not work. > >>> But if we could someway capture to the 512 MB DDR ram on the FPGA > >>> side > >>> (use it as a circular buffer) and afterwards slowly move it to > >>> the arm > >>> and from there to the host-PC then that would be fine. > >>> > >>> Alternatively I heard that high datarate (56 MSPS) capture on > >>> E310 is > >>> possible in some way using RFNoc. Is that true? How would that > work. > >>> > >>> It would help me a lot if you give me some hints or tell me about > >>> your > >>> experience of high bandwidth capturing on E3XX devices.. Even if > >>> you do > >>> not know all the answers. > >>> > >>> With best regards, > >>> > >>> Martin Dudok van Heel > >>> > >>> _______________________________________________ > >>> USRP-users mailing list -- [email protected] > >>> <mailto:[email protected]> > >>> To unsubscribe send an email to [email protected] > >>> <mailto:[email protected]> > >>> > >>> _______________________________________________ > >>> USRP-users mailing list -- [email protected] > >>> To unsubscribe send an email to [email protected] > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
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