Hi Josh, Are you using the "fpga-src" submodule in the uhd repo for your FPGA builds? If so, go into that directory and checkout the UHD-3.15.LTS tag. There is a fix on that tag for E310 builds that I think will resolve your issue. You'll need to rerun uhd_image_builder / uhd_image_builder_gui and rebuild your E310 bitstream.
Jonathon On Tue, May 4, 2021 at 8:50 AM Josh Starling <[email protected]> wrote: > Hello all, > > I’m making the transition from UHD 3.14 to 3.15 on my E310 devices. With > 3.14 I was able to successfully make FPGA images with different RFNoC > blocks combinations and correctly load them to the device. With 3.15 I’m > running into an issue where I make an image with the sig gen and digital > gain block but when I flash the device and run uhd_usrp_probe I get all the > RFNoC blocks for running fosphor (e.g. the window, FFT, forsphor, FIFO, > FIR, window, and radio blocks) . This is clean VM so there’s no old fosphor > bit files on my file system. > > Has anyone ran into any issue like this with UHD 3.15? > > The command I’ve used to flash the image is below > uhd_image_loader --args "type=e3xx,addr=192.168.50.5" --fpga-path > usrp_e310_sg3_rfnoc_fpga.bit > > Which returns that is successfully update the fpga image. I have noticed > that when I flash the stock image using the command below it returns that > it updated both the fpga image and the component dts. After flashing the > stock image uhd_usrp_probe goes back to reporting only the Radio, DUC, and > DDC blocks. > uhd_image_loader --args "type=e3xx,addr=192.168.50.5” > > I’m running this with Ubuntu 18.04 and Vivado 2018.3. Any help would be > greatly appreciated. > > Thanks > Josh > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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