Hi Paolo, Ok! I'll check on the E320 device. Thanks again.
Kind Regards, Maria. El jue, 13 may 2021 a las 12:12, Maria Muñoz (<[email protected]>) escribió: > Hi Paolo, > > Thanks for the quick answer. > > I'm sorry I forgot to say that I'm using USRP E320, but I can apply what > you explain for the X300. Thanks again! > > Looking at the X300.v file, I see that there are two other generated > clocks, one called bus_clk which is generated with the same clock reference > as ce_clk (125 MHz), and another one called radio_clk, which seems to be > referenced by a 120 MHZ clock (not sure exactly about this, but seems to be > something like that from the schematics). > > I see that radio_clk goes to the radio_block and bus_clk is related to the > Noc shell. Does this mean that my throughput would be also affected by > those clocks too? Maybe the maximum theoretical throughput could be > calculated using the lowest clock of them(which would be bus_clk in the > X300 case)? > > Kind Regards, > > Maria > > El jue, 13 may 2021 a las 10:28, Maria Muñoz (<[email protected]>) > escribió: > >> Hi all, >> >> I'm trying to size/calculate the throughput between RFNoC blocks from the >> FPGA side (not between arm/host pc and RFNoC block, which I think is the >> one the interface measure when performing uhd_usrp_probe). Is there a >> process or an existing tool to measure this throughput? >> >> Kind Regards, >> >> Maria >> >
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