Hello,
I'm trying to use an Ettus X310 with two TwinRX boards to capture signals from
four antennas with two frequency channels on each antenna, spaced about 40 MHz
apart. I've implemented this in Gnuradio Companion by capturing the whole
swath on the X310, and then filtering and downconverting to the desired
channels, but my CPU can't keep up---I get buffer overruns and large gaps in
the data.
My thought was to use RFNoC to offload the processing to the FPGA. I'm using
UHD 4.0. I've tried to build a custom image with two radios, 4 DDCs (it looks
like each DDC can handle two channels), and 4 split_stream blocks. When I try
to build the image, I get the following error:
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net
x300_core/bus_int_i/rfnoc_sandbox_i/b_split3_5/noc_shell_split_stream_i/gen_input_in[0].chdr_to_chdr_data_in_in/chdr_flusher_i/out_pipe_i/m_radio1_out_0_tready
has multiple drivers:
x300_core/bus_int_i/rfnoc_sandbox_i/b_split2_4/noc_shell_split_stream_i/gen_input_in[0].chdr_to_chdr_data_in_in/chdr_flusher_i/out_pipe_i/o_tvalid_i_3__30/O,
and
x300_core/bus_int_i/rfnoc_sandbox_i/b_split3_5/noc_shell_split_stream_i/gen_input_in[0].chdr_to_chdr_data_in_in/chdr_flusher_i/out_pipe_i/o_tvalid_i_4__18/O.
I also get a lot of warnings on most of the Xilinx tasks about unconnected
pins, some critical warnings on the final synthesis step, mostly along the
lines of "set_clock_groups:No valid object(s) found for '-group [get_clocks
bus_clk]'." I have no idea if these are to be expected.
Does this sound like the right approach for this problem? If so, what am I
doing wrong when building this?
Thanks,
Jeff
Here's my image configuration YML file:
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to
validate this file
copyright: 'Ettus Research, A National Instruments Brand' # Copyright
information used in file headers
license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information
used in file headers
version: 1.0 # File version
rfnoc_version: 1.0 # RFNoC protocol version
chdr_width: 64 # Bit width of the CHDR bus for this
image
device: 'x310'
default_target: 'X310_HG'
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 65536 # Ingress buffer size for data
ep1: # Stream endpoint name
ctrl: False # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 65536 # Ingress buffer size for data
ep2: # Stream endpoint name
ctrl: False # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 65536 # Ingress buffer size for data
ep3: # Stream endpoint name
ctrl: False # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 65536 # Ingress buffer size for data
ep4: # Stream endpoint name
ctrl: False # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 65536 # Ingress buffer size for data
ep5: # Stream endpoint name
ctrl: False # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 65536 # Ingress buffer size for data
ep6: # Stream endpoint name
ctrl: False # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 65536 # Ingress buffer size for data
ep7: # Stream endpoint name
ctrl: False # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 65536 # Ingress buffer size for data
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
radio0:
block_desc: 'radio_2x64.yml'
radio1:
block_desc: 'radio_2x64.yml'
split0:
block_desc: 'split_stream.yml'
split1:
block_desc: 'split_stream.yml'
split2:
block_desc: 'split_stream.yml'
split3:
block_desc: 'split_stream.yml'
ddc0:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
ddc1:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
ddc2:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
ddc3:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the
following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# Port A
- { srcblk: radio0, srcport: out_0, dstblk: split0, dstport: in_0 }
- { srcblk: split0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
- { srcblk: split0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
# Port B
- { srcblk: radio0, srcport: out_1, dstblk: split1, dstport: in_0 }
- { srcblk: split1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
- { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
- { srcblk: split1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
- { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
# Port C
- { srcblk: radio1, srcport: out_0, dstblk: split2, dstport: in_0 }
- { srcblk: split2, srcport: out_0, dstblk: ddc2, dstport: in_0 }
- { srcblk: ddc2, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: split2, srcport: out_1, dstblk: ddc2, dstport: in_1 }
- { srcblk: ddc2, srcport: out_1, dstblk: ep5, dstport: in0 }
# Port D
- { srcblk: radio1, srcport: out_0, dstblk: split3, dstport: in_0 }
- { srcblk: split3, srcport: out_0, dstblk: ddc3, dstport: in_0 }
- { srcblk: ddc3, srcport: out_0, dstblk: ep6, dstport: in0 }
- { srcblk: split3, srcport: out_1, dstblk: ddc3, dstport: in_1 }
- { srcblk: ddc3, srcport: out_1, dstblk: ep7, dstport: in0 }
# BSP Connections
- { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport:
ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport:
ctrlport_radio1 }
- { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport:
x300_radio }
- { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport:
x300_radio }
- { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport:
time_keeper }
- { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport:
time_keeper }
# A list of all clock domain connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the
following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc2, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc3, dstport: ce }
_______________________________________________
USRP-users mailing list -- [email protected]
To unsubscribe send an email to [email protected]
