Hi, Marcus, Thanks for your reply. The clear & precise problem description is an endless pursuit I should try to do better. My experience is a lot of problem get answered by itself when it is described clear enough to the very detail, it’s part of a learning process.
My current guess is the FPGA program after JTAG download runs the ZPU to retrieve the existing settings, such as the IP, from EEPROM. The page(s) for setting must live outside the pages used for FPGA image, as the uhd_image_loader process won’t change these settings. This is another entry in my TODO list. Wish everybody a nice weekend.
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