I'm trying to run the testbench for a new module I created (UHD4) and I'm getting the following error:
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/nvd/uhd/fpga/usrp3/lib/control/gray2bin.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module gray2bin ERROR: [VRFC 10-1103] net type must be explicitly specified for 'gray' when default_nettype is none [/home/nvd/uhd/fpga/usrp3/lib/control/gray2bin.v:13] ERROR: [VRFC 10-3594] non-net port 'gray' cannot be of mode input [/home/nvd/uhd/fpga/usrp3/lib/control/gray2bin.v:13] ERROR: [VRFC 10-845] illegal operand for operator ^ [/home/nvd/uhd/fpga/usrp3/lib/control/gray2bin.v:21] ERROR: [VRFC 10-2865] module 'gray2bin' ignored due to previous errors [/home/nvd/uhd/fpga/usrp3/lib/control/gray2bin.v:10] This file seems to compile without issue on my previous testbench, so I'm not sure what the difference would be here. If anyone has any insights into what could be going on I'd greatly appreciate it. Thank you, Michael H. Rich Electronic Systems Laboratory Georgia Tech Research InstituteR Phone: (404) 407-8358 E-mail: <mailto:[email protected]> [email protected]
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